Lines Matching refs:Rd
1522 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1529 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1530 iii, opc, "\t$Rd, $Rn, $imm",
1531 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1533 bits<4> Rd;
1538 let Inst{15-12} = Rd;
1542 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1543 iir, opc, "\t$Rd, $Rn, $Rm",
1544 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1546 bits<4> Rd;
1552 let Inst{15-12} = Rd;
1557 def rsi : AsI1<opcod, (outs GPR:$Rd),
1559 iis, opc, "\t$Rd, $Rn, $shift",
1560 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1562 bits<4> Rd;
1567 let Inst{15-12} = Rd;
1573 def rsr : AsI1<opcod, (outs GPR:$Rd),
1575 iis, opc, "\t$Rd, $Rn, $shift",
1576 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1578 bits<4> Rd;
1583 let Inst{15-12} = Rd;
1595 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1602 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1603 iii, opc, "\t$Rd, $Rn, $imm",
1604 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1606 bits<4> Rd;
1611 let Inst{15-12} = Rd;
1615 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1616 iir, opc, "\t$Rd, $Rn, $Rm",
1619 bits<4> Rd;
1625 let Inst{15-12} = Rd;
1629 def rsi : AsI1<opcod, (outs GPR:$Rd),
1631 iis, opc, "\t$Rd, $Rn, $shift",
1632 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1634 bits<4> Rd;
1639 let Inst{15-12} = Rd;
1645 def rsr : AsI1<opcod, (outs GPR:$Rd),
1647 iis, opc, "\t$Rd, $Rn, $shift",
1648 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1650 bits<4> Rd;
1655 let Inst{15-12} = Rd;
1672 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1674 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1677 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1679 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1683 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1686 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1690 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1693 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1704 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1706 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1709 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1712 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1716 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1719 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1808 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1809 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1810 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1812 bits<4> Rd;
1816 let Inst{15-12} = Rd;
1822 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1823 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1833 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1834 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1835 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1838 bits<4> Rd;
1843 let Inst{15-12} = Rd;
1850 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1851 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1860 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1864 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1865 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1866 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1869 bits<4> Rd;
1873 let Inst{15-12} = Rd;
1877 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1878 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1879 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1882 bits<4> Rd;
1889 let Inst{15-12} = Rd;
1892 def rsi : AsI1<opcod, (outs GPR:$Rd),
1894 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1895 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1898 bits<4> Rd;
1903 let Inst{15-12} = Rd;
1908 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1910 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1911 [(set GPRnopc:$Rd, CPSR,
1915 bits<4> Rd;
1920 let Inst{15-12} = Rd;
1931 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1934 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1935 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1936 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1939 bits<4> Rd;
1943 let Inst{15-12} = Rd;
1947 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1948 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1951 bits<4> Rd;
1957 let Inst{15-12} = Rd;
1960 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1961 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1962 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1965 bits<4> Rd;
1970 let Inst{15-12} = Rd;
1975 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1976 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1977 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1980 bits<4> Rd;
1985 let Inst{15-12} = Rd;
2192 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2193 "\t$Rd, $Rn, $Rm",
2194 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2196 bits<4> Rd;
2200 let Inst{15-12} = Rd;
2412 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2413 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2415 bits<4> Rd;
2423 let Inst{15-12} = Rd;
2428 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2431 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
3572 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3573 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3574 bits<4> Rd;
3581 let Inst{15-12} = Rd;
3586 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3587 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3588 bits<4> Rd;
3594 let Inst{15-12} = Rd;
3597 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3599 "mov", "\t$Rd, $src",
3600 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3602 bits<4> Rd;
3604 let Inst{15-12} = Rd;
3614 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3616 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3618 bits<4> Rd;
3620 let Inst{15-12} = Rd;
3629 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3630 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3632 bits<4> Rd;
3635 let Inst{15-12} = Rd;
3641 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3643 "movw", "\t$Rd, $imm",
3644 [(set GPR:$Rd, imm0_65535:$imm)]>,
3646 bits<4> Rd;
3648 let Inst{15-12} = Rd;
3656 def : InstAlias<"mov${p} $Rd, $imm",
3657 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
3662 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3666 let Constraints = "$src = $Rd" in {
3667 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3670 "movt", "\t$Rd, $imm",
3671 [(set GPRnopc:$Rd,
3675 bits<4> Rd;
3677 let Inst{15-12} = Rd;
3687 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3697 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3698 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3789 def SBFX : I<(outs GPRnopc:$Rd),
3792 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3794 bits<4> Rd;
3801 let Inst{15-12} = Rd;
3806 def UBFX : I<(outs GPRnopc:$Rd),
3809 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3811 bits<4> Rd;
3818 let Inst{15-12} = Rd;
3906 string asm = "\t$Rd, $Rn, $Rm">
3907 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3910 bits<4> Rd;
3915 let Inst{15-12} = Rd;
3927 "\t$Rd, $Rm, $Rn">;
3932 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
3942 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm,
3945 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm,
3948 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
3951 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
4023 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4025 "\t$Rd, $Rn, $Rm",
4026 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4028 bits<4> Rd;
4034 let Inst{19-16} = Rd;
4038 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4040 "\t$Rd, $Rn, $Rm, $Ra",
4041 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4043 bits<4> Rd;
4049 let Inst{19-16} = Rd;
4056 def SSAT : AI<(outs GPRnopc:$Rd),
4058 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4060 bits<4> Rd;
4067 let Inst{15-12} = Rd;
4073 def SSAT16 : AI<(outs GPRnopc:$Rd),
4075 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
4077 bits<4> Rd;
4082 let Inst{15-12} = Rd;
4087 def USAT : AI<(outs GPRnopc:$Rd),
4089 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4091 bits<4> Rd;
4097 let Inst{15-12} = Rd;
4104 def USAT16 : AI<(outs GPRnopc:$Rd),
4106 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
4108 bits<4> Rd;
4113 let Inst{15-12} = Rd;
4166 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
4168 "bfc", "\t$Rd, $imm", "$src = $Rd",
4169 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
4171 bits<4> Rd;
4175 let Inst{15-12} = Rd;
4181 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4183 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
4184 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4187 bits<4> Rd;
4192 let Inst{15-12} = Rd;
4198 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
4199 "mvn", "\t$Rd, $Rm",
4200 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4201 bits<4> Rd;
4206 let Inst{15-12} = Rd;
4211 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
4212 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
4213 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
4215 bits<4> Rd;
4219 let Inst{15-12} = Rd;
4226 def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
4227 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
4228 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
4230 bits<4> Rd;
4234 let Inst{15-12} = Rd;
4244 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
4245 IIC_iMVNi, "mvn", "\t$Rd, $imm",
4246 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
4247 bits<4> Rd;
4251 let Inst{15-12} = Rd;
4265 bits<4> Rd;
4268 let Inst{19-16} = Rd;
4300 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
4301 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
4303 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
4304 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
4311 let Constraints = "@earlyclobber $Rd" in
4312 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
4315 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
4316 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
4321 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
4323 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4324 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4331 let Constraints = "@earlyclobber $Rd" in
4332 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
4335 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
4336 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
4340 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4341 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
4342 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4345 bits<4> Rd;
4349 let Inst{19-16} = Rd;
4444 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4445 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
4446 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4452 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4453 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
4454 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4460 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4462 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
4463 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4467 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4469 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
4470 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4474 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
4476 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4480 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4482 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
4483 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4488 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4489 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4490 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4494 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4495 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4496 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4500 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4501 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4502 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4506 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4507 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4508 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4512 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4513 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4514 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4518 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4519 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4520 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4528 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4530 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4531 [(set GPRnopc:$Rd, (add GPR:$Ra,
4536 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4538 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4539 [(set GPRnopc:$Rd, (add GPR:$Ra,
4544 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4546 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4547 [(set GPRnopc:$Rd, (add GPR:$Ra,
4552 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4554 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4555 [(set GPRnopc:$Rd, (add GPR:$Ra,
4560 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4562 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4563 [(set GPRnopc:$Rd,
4568 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4570 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4571 [(set GPRnopc:$Rd,
4625 bits<4> Rd;
4627 let Inst{19-16} = Rd;
4633 bits<4> Rd;
4634 let Inst{19-16} = Rd;
4648 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4650 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
4653 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4655 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
4695 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4696 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
4698 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4699 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
4718 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4719 "sdiv", "\t$Rd, $Rn, $Rm",
4720 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4724 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4725 "udiv", "\t$Rd, $Rn, $Rm",
4726 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4734 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4735 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4736 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4739 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4740 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4741 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4745 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4746 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4747 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4751 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4752 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4753 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4765 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4766 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4767 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4775 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4777 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4778 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4792 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4794 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4795 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4824 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4825 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4826 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4828 bits<4> Rd;
4837 let Inst{15-12} = Rd;
5007 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
5010 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
5012 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5014 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
5017 [(set GPR:$Rd,
5020 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5021 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
5024 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
5026 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5031 : ARMPseudoInst<(outs GPR:$Rd),
5034 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
5036 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
5040 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
5043 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
5045 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5050 : ARMPseudoInst<(outs GPR:$Rd),
5053 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
5055 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
5058 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
5061 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
5063 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5257 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
5258 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5259 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
5260 [(set GPR:$Rd, (strex_1 GPR:$Rt,
5262 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5263 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
5264 [(set GPR:$Rd, (strex_2 GPR:$Rt,
5266 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5267 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
5268 [(set GPR:$Rd, (strex_4 GPR:$Rt,
5271 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
5273 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
5276 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5277 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
5278 [(set GPR:$Rd,
5280 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5281 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
5282 [(set GPR:$Rd,
5284 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5285 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
5286 [(set GPR:$Rd,
5289 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
5291 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
5746 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5747 "mrs", "\t$Rd, apsr", []> {
5748 bits<4> Rd;
5752 let Inst{15-12} = Rd;
5758 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
5763 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5764 "mrs", "\t$Rd, spsr", []> {
5765 bits<4> Rd;
5769 let Inst{15-12} = Rd;
5777 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5778 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5781 bits<4> Rd;
5787 let Inst{15-12} = Rd;
6220 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
6221 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
6223 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
6224 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
6232 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
6233 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6234 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
6235 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6239 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
6240 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6241 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
6242 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6243 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
6244 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6245 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
6246 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6247 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
6248 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6249 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
6250 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6252 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
6253 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6254 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
6255 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6256 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
6257 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6258 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
6259 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6260 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
6261 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6262 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
6263 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6303 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
6305 def : ARMInstSubst<"mov${s}${p} $Rd, $imm",
6306 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6307 def : ARMInstSubst<"mvn${s}${p} $Rd, $imm",
6308 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6310 def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm",
6311 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6316 def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm",
6317 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6323 // Likewise, "add Rd, mod_imm_neg" -> sub
6324 def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm",
6325 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6326 def : ARMInstSubst<"add${s}${p} $Rd, $imm",
6327 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6328 // Likewise, "sub Rd, mod_imm_neg" -> add
6329 def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm",
6330 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6331 def : ARMInstSubst<"sub${s}${p} $Rd, $imm",
6332 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6335 def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm",
6336 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6339 def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm",
6340 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6345 def : ARMInstSubst<"cmp${p} $Rd, $imm",
6346 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
6347 def : ARMInstSubst<"cmn${p} $Rd, $imm",
6348 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
6355 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
6356 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
6357 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6359 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
6360 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6362 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
6363 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6365 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
6366 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6369 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
6370 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
6371 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
6372 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
6373 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6375 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
6376 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6378 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
6379 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6381 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
6382 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6387 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
6388 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6397 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
6398 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
6400 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
6401 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
6422 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6424 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;
6453 let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
6455 def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6459 def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6463 def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6467 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),