Lines Matching refs:IsARM
1811 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1824 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1837 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1852 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1867 Requires<[IsARM]>,
1880 Requires<[IsARM]>,
1896 Requires<[IsARM]>,
1913 Requires<[IsARM]>,
1937 Requires<[IsARM]>,
1963 Requires<[IsARM]>,
1978 Requires<[IsARM]>,
2176 Requires<[IsARM, HasV6]> {
2183 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
2184 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
2185 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
2186 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
2187 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
2188 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
2189 def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
2190 def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>;
2195 Requires<[IsARM, HasV6]> {
2211 "bkpt", "\t$val", []>, Requires<[IsARM]> {
2220 def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>;
2223 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
2236 []>, Requires<[IsARM]> {
2301 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
2302 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
2303 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2306 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2314 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2351 Requires<[IsARM,UseNaClTrap]> {
2357 Requires<[IsARM,DontUseNaClTrap]> {
2361 def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>;
2362 def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>;
2444 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2451 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2467 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2475 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2492 Requires<[IsARM]>, Sched<[WriteBrL]> {
2502 Requires<[IsARM]>, Sched<[WriteBrL]> {
2510 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2517 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>;
2522 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2530 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>;
2537 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2542 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2548 Requires<[IsARM]>, Sched<[WriteBr]>;
2554 Requires<[IsARM]>, Sched<[WriteBr]>;
2558 Requires<[IsARM, HasV5T, NoSLSBLRMitigation]>;
2560 Requires<[IsARM, HasV5T, SLSBLRMitigation]>;
2562 Requires<[IsARM, HasV5T, NoSLSBLRMitigation]>;
2564 Requires<[IsARM, HasV5T, SLSBLRMitigation]>;
2619 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2651 Requires<[IsARM]>, Sched<[WriteBr]>;
2656 Requires<[IsARM, HasV4T]>;
2661 []>, Requires<[IsARM, HasTrustZone]> {
2772 Requires<[IsARM, HasVirtualization]> {
2791 Requires<[IsARM, HasVirtualization]> {
2841 Requires<[IsARM, HasV5TE]>;
2847 Requires<[IsARM, HasV5TE]> {
3125 Requires<[IsARM, HasV5TE]> {
3133 Requires<[IsARM, HasV5TE]> {
3645 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3658 Requires<[IsARM, HasV6T2]>;
3674 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3694 Requires<[IsARM, HasV6T2]>;
3699 Requires<[IsARM]>, Sched<[WriteALU]>;
3707 Sched<[WriteALU]>, Requires<[IsARM]>;
3710 Sched<[WriteALU]>, Requires<[IsARM]>;
3793 Requires<[IsARM, HasV6T2]> {
3810 Requires<[IsARM, HasV6T2]> {
3881 Requires<[IsARM, HasV6T2]>;
3884 Requires<[IsARM, HasV6T2]>;
3893 Requires<[IsARM, HasV6T2]>;
4027 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
4042 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
4059 Requires<[IsARM,HasV6]>{
4076 Requires<[IsARM,HasV6]>{
4090 Requires<[IsARM,HasV6]> {
4107 Requires<[IsARM,HasV6]>{
4170 Requires<[IsARM, HasV6T2]> {
4186 Requires<[IsARM, HasV6T2]> {
4305 Requires<[IsARM, HasV6]>,
4317 Requires<[IsARM, NoV6, UseMulOps]>,
4325 Requires<[IsARM, HasV6, UseMulOps]>,
4337 Requires<[IsARM, NoV6]>,
4343 Requires<[IsARM, HasV6T2, UseMulOps]>,
4363 Requires<[IsARM, HasV6]>,
4371 Requires<[IsARM, HasV6]>,
4381 Requires<[IsARM, NoV6]>,
4390 Requires<[IsARM, NoV6]>,
4399 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4404 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4411 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4430 Requires<[IsARM, NoV6]>,
4437 Requires<[IsARM, NoV6]>,
4447 Requires<[IsARM, HasV6]>,
4455 Requires<[IsARM, HasV6]>,
4464 Requires<[IsARM, HasV6, UseMulOps]>,
4471 Requires<[IsARM, HasV6]>,
4477 Requires<[IsARM, HasV6, UseMulOps]>,
4484 Requires<[IsARM, HasV6]>,
4491 Requires<[IsARM, HasV5TE]>,
4497 Requires<[IsARM, HasV5TE]>,
4503 Requires<[IsARM, HasV5TE]>,
4509 Requires<[IsARM, HasV5TE]>,
4515 Requires<[IsARM, HasV5TE]>,
4521 Requires<[IsARM, HasV5TE]>,
4533 Requires<[IsARM, HasV5TE, UseMulOps]>,
4541 Requires<[IsARM, HasV5TE, UseMulOps]>,
4549 Requires<[IsARM, HasV5TE, UseMulOps]>,
4557 Requires<[IsARM, HasV5TE, UseMulOps]>,
4565 Requires<[IsARM, HasV5TE, UseMulOps]>,
4573 Requires<[IsARM, HasV5TE, UseMulOps]>,
4588 Requires<[IsARM, HasV5TE]>,
4609 Requires<[IsARM, HasV6]> {
4721 Requires<[IsARM, HasDivideInARM]>,
4727 Requires<[IsARM, HasDivideInARM]>,
4736 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4742 Requires<[IsARM, HasV6T2]>,
4747 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4754 Requires<[IsARM, HasV6]>,
4768 Requires<[IsARM, HasV6]>,
4781 Requires<[IsARM, HasV6]>,
4798 Requires<[IsARM, HasV6]>,
4827 Requires<[IsARM, HasV8, HasCRC]> {
4860 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
5036 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
5055 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
5105 Requires<[IsARM, HasDB]> {
5113 Requires<[IsARM, HasDB]> {
5122 Requires<[IsARM, HasDB]> {
5130 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> {
5139 Requires<[IsARM, HasSB]>, Sched<[]> {
5298 Requires<[IsARM, HasV6K]> {
5346 Requires<[IsARM,PreV8]>;
5349 Requires<[IsARM,PreV8]>;
5361 Requires<[IsARM,PreV8]> {
5385 Requires<[IsARM,PreV8]> {
5569 …Cop<1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5570 …p<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5574 …Cop<0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5575 …p<0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
5660 Requires<[IsARM,PreV8]>;
5668 Requires<[IsARM,PreV8]>;
5711 Requires<[IsARM,PreV8]> {
5759 Requires<[IsARM]>;
5779 Requires<[IsARM, HasVirtualization]> {
5833 Requires<[IsARM, HasVirtualization]> {
5880 Requires<[IsARM, IsReadTPSoft]>;
5885 Requires<[IsARM, IsReadTPHard]>;
5911 Requires<[IsARM, HasVFP2]>;
5921 Requires<[IsARM, NoVFP]>;
5931 Requires<[IsARM]>;
5955 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5961 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5972 Requires<[IsARM]>;
5976 Requires<[IsARM, DontUseMovt]>;
5986 Requires<[IsARM, UseMovtInPic]>;
5992 Requires<[IsARM, DontUseMovtInPic]>;
5999 Requires<[IsARM, DontUseMovtInPic]>;
6005 Requires<[IsARM, UseMovtInPic]>;
6011 Requires<[IsARM, UseMovt]>;
6015 Requires<[IsARM, DontUseMovt]>;
6018 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>;
6022 Requires<[IsARM, DontUseMovtInPic]>;
6026 Requires<[IsARM, UseMovtInPic]>;
6032 Requires<[IsARM, UseMovt]>;
6034 Requires<[IsARM, UseMovt]>;
6114 Requires<[IsARM, HasV6]>;
6199 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
6200 def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
6201 def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>;
6202 def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>;
6203 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
6205 def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>;
6222 Requires<[IsARM, HasV6]>;
6225 Requires<[IsARM, HasV6]>;
6392 Requires<[IsARM, NoV6]>;
6399 Requires<[IsARM, NoV6]>;
6403 Requires<[IsARM, NoV6]>;
6406 Requires<[IsARM, NoV6]>;
6409 Requires<[IsARM, NoV6]>;
6412 Requires<[IsARM, NoV6]>;
6415 Requires<[IsARM, NoV6]>;