Lines Matching refs:Ops
234 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
237 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
241 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc);
243 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, EVT InactiveTy);
1638 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1641 MVT::Other, Ops); in tryARMIndexedLoad()
1648 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1651 MVT::Other, Ops); in tryARMIndexedLoad()
1679 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)), in tryT1IndexedLoad() local
1682 MVT::i32, MVT::Other, Ops); in tryT1IndexedLoad()
1727 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)), in tryT2IndexedLoad() local
1730 MVT::Other, Ops); in tryT2IndexedLoad()
1823 SDValue Ops[] = {Base, in tryMVEIndexedLoad() local
1830 N->getValueType(0), MVT::Other, Ops); in tryMVEIndexedLoad()
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode() local
1847 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode() local
1858 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode() local
1869 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createDRegPairNode()
1879 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode() local
1880 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQRegPairNode()
1893 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode() local
1895 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadSRegsNode()
1908 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode() local
1910 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadDRegsNode()
1923 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadQRegsNode() local
1925 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadQRegsNode()
2162 SmallVector<SDValue, 7> Ops; in SelectVLD() local
2168 Ops.push_back(MemAddr); in SelectVLD()
2169 Ops.push_back(Align); in SelectVLD()
2178 Ops.push_back(Inc); in SelectVLD()
2182 Ops.push_back(Reg0); in SelectVLD()
2184 Ops.push_back(Pred); in SelectVLD()
2185 Ops.push_back(Reg0); in SelectVLD()
2186 Ops.push_back(Chain); in SelectVLD()
2187 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLD()
2204 Ops.push_back(SDValue(VLdA, 1)); in SelectVLD()
2205 Ops.push_back(Align); in SelectVLD()
2211 Ops.push_back(Reg0); in SelectVLD()
2213 Ops.push_back(SDValue(VLdA, 0)); in SelectVLD()
2214 Ops.push_back(Pred); in SelectVLD()
2215 Ops.push_back(Reg0); in SelectVLD()
2216 Ops.push_back(Chain); in SelectVLD()
2217 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops); in SelectVLD()
2296 SmallVector<SDValue, 7> Ops; in SelectVST() local
2327 Ops.push_back(MemAddr); in SelectVST()
2328 Ops.push_back(Align); in SelectVST()
2337 Ops.push_back(Inc); in SelectVST()
2342 Ops.push_back(Reg0); in SelectVST()
2344 Ops.push_back(SrcReg); in SelectVST()
2345 Ops.push_back(Pred); in SelectVST()
2346 Ops.push_back(Reg0); in SelectVST()
2347 Ops.push_back(Chain); in SelectVST()
2348 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVST()
2379 Ops.push_back(SDValue(VStA, 0)); in SelectVST()
2380 Ops.push_back(Align); in SelectVST()
2386 Ops.push_back(Reg0); in SelectVST()
2388 Ops.push_back(RegSeq); in SelectVST()
2389 Ops.push_back(Pred); in SelectVST()
2390 Ops.push_back(Reg0); in SelectVST()
2391 Ops.push_back(Chain); in SelectVST()
2393 Ops); in SelectVST()
2470 SmallVector<SDValue, 8> Ops; in SelectVLDSTLane() local
2471 Ops.push_back(MemAddr); in SelectVLDSTLane()
2472 Ops.push_back(Align); in SelectVLDSTLane()
2477 Ops.push_back(IsImmUpdate ? Reg0 : Inc); in SelectVLDSTLane()
2498 Ops.push_back(SuperReg); in SelectVLDSTLane()
2499 Ops.push_back(getI32Imm(Lane, dl)); in SelectVLDSTLane()
2500 Ops.push_back(Pred); in SelectVLDSTLane()
2501 Ops.push_back(Reg0); in SelectVLDSTLane()
2502 Ops.push_back(Chain); in SelectVLDSTLane()
2506 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDSTLane()
2529 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, in AddMVEPredicateToOps() argument
2531 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32)); in AddMVEPredicateToOps()
2532 Ops.push_back(PredicateMask); in AddMVEPredicateToOps()
2533 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddMVEPredicateToOps()
2537 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, in AddMVEPredicateToOps() argument
2540 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32)); in AddMVEPredicateToOps()
2541 Ops.push_back(PredicateMask); in AddMVEPredicateToOps()
2542 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddMVEPredicateToOps()
2543 Ops.push_back(Inactive); in AddMVEPredicateToOps()
2547 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) { in AddEmptyMVEPredicateToOps() argument
2548 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32)); in AddEmptyMVEPredicateToOps()
2549 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in AddEmptyMVEPredicateToOps()
2550 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddEmptyMVEPredicateToOps()
2554 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, in AddEmptyMVEPredicateToOps() argument
2556 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32)); in AddEmptyMVEPredicateToOps()
2557 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in AddEmptyMVEPredicateToOps()
2558 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddEmptyMVEPredicateToOps()
2559 Ops.push_back(SDValue( in AddEmptyMVEPredicateToOps()
2566 SmallVector<SDValue, 8> Ops; in SelectMVE_WB() local
2580 Ops.push_back(N->getOperand(2)); // vector of base addresses in SelectMVE_WB()
2583 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate offset in SelectMVE_WB()
2586 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4)); in SelectMVE_WB()
2588 AddEmptyMVEPredicateToOps(Ops, Loc); in SelectMVE_WB()
2590 Ops.push_back(N->getOperand(0)); // chain in SelectMVE_WB()
2597 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), VTs, Ops); in SelectMVE_WB()
2609 SmallVector<SDValue, 8> Ops; in SelectMVE_LongShift() local
2612 Ops.push_back(N->getOperand(1)); in SelectMVE_LongShift()
2613 Ops.push_back(N->getOperand(2)); in SelectMVE_LongShift()
2618 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count in SelectMVE_LongShift()
2620 Ops.push_back(N->getOperand(3)); in SelectMVE_LongShift()
2627 Ops.push_back(getI32Imm(SatBit, Loc)); in SelectMVE_LongShift()
2632 Ops.push_back(getAL(CurDAG, Loc)); in SelectMVE_LongShift()
2633 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in SelectMVE_LongShift()
2635 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops)); in SelectMVE_LongShift()
2642 SmallVector<SDValue, 8> Ops; in SelectMVE_VADCSBC() local
2648 Ops.push_back(N->getOperand(FirstInputOp)); in SelectMVE_VADCSBC()
2649 Ops.push_back(N->getOperand(FirstInputOp + 1)); in SelectMVE_VADCSBC()
2658 Ops.push_back(CarryIn); in SelectMVE_VADCSBC()
2663 AddMVEPredicateToOps(Ops, Loc, in SelectMVE_VADCSBC()
2667 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0)); in SelectMVE_VADCSBC()
2669 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops)); in SelectMVE_VADCSBC()
2674 SmallVector<SDValue, 8> Ops; in SelectMVE_VSHLC() local
2678 Ops.push_back(N->getOperand(1)); in SelectMVE_VSHLC()
2679 Ops.push_back(N->getOperand(2)); in SelectMVE_VSHLC()
2681 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count in SelectMVE_VSHLC()
2684 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4)); in SelectMVE_VSHLC()
2686 AddEmptyMVEPredicateToOps(Ops, Loc); in SelectMVE_VSHLC()
2688 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), makeArrayRef(Ops)); in SelectMVE_VSHLC()
2735 SmallVector<SDValue, 8> Ops; in SelectBaseMVE_VMLLDAV() local
2738 Ops.push_back(N->getOperand(4)); in SelectBaseMVE_VMLLDAV()
2739 Ops.push_back(N->getOperand(5)); in SelectBaseMVE_VMLLDAV()
2742 Ops.push_back(N->getOperand(6)); in SelectBaseMVE_VMLLDAV()
2743 Ops.push_back(N->getOperand(7)); in SelectBaseMVE_VMLLDAV()
2746 AddMVEPredicateToOps(Ops, Loc, N->getOperand(8)); in SelectBaseMVE_VMLLDAV()
2748 AddEmptyMVEPredicateToOps(Ops, Loc); in SelectBaseMVE_VMLLDAV()
2750 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops)); in SelectBaseMVE_VMLLDAV()
2812 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain}; in SelectMVE_VLD() local
2814 CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops); in SelectMVE_VLD()
2822 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain}; in SelectMVE_VLD() local
2824 CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops); in SelectMVE_VLD()
2858 SmallVector<SDValue, 8> Ops; in SelectMVE_VxDUP() local
2865 Ops.push_back(N->getOperand(OpIdx++)); // base in SelectMVE_VxDUP()
2867 Ops.push_back(N->getOperand(OpIdx++)); // limit in SelectMVE_VxDUP()
2871 Ops.push_back(getI32Imm(ImmValue, Loc)); in SelectMVE_VxDUP()
2874 AddMVEPredicateToOps(Ops, Loc, N->getOperand(OpIdx), Inactive); in SelectMVE_VxDUP()
2876 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0)); in SelectMVE_VxDUP()
2878 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops)); in SelectMVE_VxDUP()
2885 SmallVector<SDValue, 8> Ops; in SelectCDE_CXxD() local
2892 Ops.push_back(getI32Imm(ImmCoprocVal, Loc)); in SelectCDE_CXxD()
2901 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0)); in SelectCDE_CXxD()
2906 Ops.push_back(N->getOperand(OpIdx++)); in SelectCDE_CXxD()
2911 Ops.push_back(getI32Imm(ImmVal, Loc)); in SelectCDE_CXxD()
2917 Ops.push_back(Pred); in SelectCDE_CXxD()
2918 Ops.push_back(PredReg); in SelectCDE_CXxD()
2922 SDNode *InstrNode = CurDAG->getMachineNode(Opcode, Loc, MVT::Untyped, Ops); in SelectCDE_CXxD()
3011 SmallVector<SDValue, 6> Ops; in SelectVLDDup() local
3012 Ops.push_back(MemAddr); in SelectVLDDup()
3013 Ops.push_back(Align); in SelectVLDDup()
3023 Ops.push_back(Reg0); in SelectVLDDup()
3027 Ops.push_back(Inc); in SelectVLDDup()
3043 Ops.push_back(SDValue(VLdA, 0)); in SelectVLDDup()
3047 Ops.push_back(Pred); in SelectVLDDup()
3048 Ops.push_back(Reg0); in SelectVLDDup()
3049 Ops.push_back(Chain); in SelectVLDDup()
3051 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDDup()
3241 SmallVector<SDValue, 3> Ops{ in transformFixedFloatingPointConversion() local
3243 AddEmptyMVEPredicateToOps(Ops, SDLoc(N), Type); in transformFixedFloatingPointConversion()
3264 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), Type, Ops)); in transformFixedFloatingPointConversion()
3301 SmallVector<SDValue, 3> Ops{Node->getOperand(0), in tryFP_TO_INT() local
3303 AddEmptyMVEPredicateToOps(Ops, dl, Type); in tryFP_TO_INT()
3305 ReplaceNode(N, CurDAG->getMachineNode(Opcode, dl, Type, Ops)); in tryFP_TO_INT()
3369 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3372 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3381 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp() local
3383 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3388 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3392 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3413 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3417 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3435 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3439 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3456 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3460 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3519 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3), in SelectCMP_SWAP() local
3523 CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
3576 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32), in SelectCMPZ() local
3579 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in SelectCMPZ()
3581 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ() local
3584 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in SelectCMPZ()
3646 SDValue Ops[] = {ST->getValue(), in Select() local
3653 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops); in Select()
3691 SDValue Ops[] = { in Select() local
3698 Ops); in Select()
3700 SDValue Ops[] = { in Select() local
3708 Ops); in Select()
3744 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32), in Select() local
3747 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in Select()
3791 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select() local
3792 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
3795 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select() local
3797 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
3810 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select() local
3811 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
3814 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select() local
3816 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
3853 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select() local
3856 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
3859 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl), in Select() local
3863 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
3898 SDValue Ops[] = { N0.getOperand(0), Imm16, in Select() local
3900 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops)); in Select()
3909 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
3913 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops)); in Select()
3918 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3922 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3925 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3931 MVT::i32, MVT::i32, Ops)); in Select()
3937 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3941 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3944 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3950 MVT::i32, MVT::i32, Ops)); in Select()
3979 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1), in Select() local
3982 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops)); in Select()
4020 SDValue Ops[] = { N->getOperand(1), in Select() local
4024 SDNode *New = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops); in Select()
4044 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select() local
4046 {MVT::Untyped, MVT::Other}, Ops); in Select()
4075 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select() local
4076 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops); in Select()
4083 SDValue Ops[] = { N->getOperand(1), in Select() local
4088 CurDAG->getVTList(MVT::i32, MVT::Other), Ops); in Select()
4168 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; in Select() local
4170 MVT::Glue, Ops); in Select()
4199 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32), in Select() local
4202 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
4205 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select() local
4208 Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in Select()
4242 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc, in Select() local
4244 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops); in Select()
4271 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
4272 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
4294 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
4295 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
4316 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
4317 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
4749 SmallVector<SDValue, 5> Ops; in Select() local
4750 … Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */ in Select()
4751 … Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */ in Select()
4752 … Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */ in Select()
4758 Ops.push_back(getAL(CurDAG, dl)); in Select()
4759 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
4762 Ops.push_back(Chain); in Select()
4767 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops)); in Select()
4791 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl), in Select() local
4793 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
4844 SmallVector<SDValue, 7> Ops; in Select() local
4846 Ops.push_back(Val0); in Select()
4847 Ops.push_back(Val1); in Select()
4850 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); in Select()
4851 Ops.push_back(MemAddr); in Select()
4852 Ops.push_back(getAL(CurDAG, dl)); in Select()
4853 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
4854 Ops.push_back(Chain); in Select()
4860 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
5211 SDValue Ops[] = { Src, Src, Pred, Reg0 }; in Select() local
5212 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops); in Select()
5222 SDValue Ops[] = { Src, Pred, Reg0 }; in Select() local
5223 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops); in Select()
5391 std::vector<SDValue> &Ops) { in getIntOperandsFromRegisterString() argument
5402 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32)); in getIntOperandsFromRegisterString()
5514 std::vector<SDValue> Ops; in tryReadRegister() local
5515 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops); in tryReadRegister()
5517 if (!Ops.empty()) { in tryReadRegister()
5524 if (Ops.size() == 5){ in tryReadRegister()
5528 assert(Ops.size() == 3 && in tryReadRegister()
5534 Ops.push_back(getAL(CurDAG, DL)); in tryReadRegister()
5535 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in tryReadRegister()
5536 Ops.push_back(N->getOperand(0)); in tryReadRegister()
5537 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops)); in tryReadRegister()
5545 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), in tryReadRegister()
5550 DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5575 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
5578 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5590 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32), in tryReadRegister() local
5594 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5601 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
5604 DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5609 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
5613 MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5629 std::vector<SDValue> Ops; in tryWriteRegister() local
5630 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops); in tryWriteRegister()
5632 if (!Ops.empty()) { in tryWriteRegister()
5638 if (Ops.size() == 5) { in tryWriteRegister()
5640 Ops.insert(Ops.begin()+2, N->getOperand(2)); in tryWriteRegister()
5642 assert(Ops.size() == 3 && in tryWriteRegister()
5646 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2); in tryWriteRegister()
5649 Ops.push_back(getAL(CurDAG, DL)); in tryWriteRegister()
5650 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in tryWriteRegister()
5651 Ops.push_back(N->getOperand(0)); in tryWriteRegister()
5653 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryWriteRegister()
5660 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2), in tryWriteRegister()
5665 DL, MVT::Other, Ops)); in tryWriteRegister()
5683 Ops = { N->getOperand(2), getAL(CurDAG, DL), in tryWriteRegister()
5685 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryWriteRegister()
5701 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32), in tryWriteRegister() local
5704 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
5713 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2), in tryWriteRegister()
5717 DL, MVT::Other, Ops)); in tryWriteRegister()
5830 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1); in tryInlineAsm() local
5831 Ops.push_back(T1.getValue(1)); in tryInlineAsm()
5832 CurDAG->UpdateNodeOperands(GU, Ops); in tryInlineAsm()