2648         /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },  in ARMEmitIntExt()
2649         /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },  in ARMEmitIntExt()
2650         /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },  in ARMEmitIntExt()
2651         /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },  in ARMEmitIntExt()
2652         /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },  in ARMEmitIntExt()
2653         /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }  in ARMEmitIntExt()
2658         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2659         /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },  in ARMEmitIntExt()
2660         /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2661         /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },  in ARMEmitIntExt()
2662         /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2663         /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }  in ARMEmitIntExt()
2666         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2667         /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },  in ARMEmitIntExt()
2668         /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2669         /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },  in ARMEmitIntExt()
2670         /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2671         /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }  in ARMEmitIntExt()
2696   assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&  in ARMEmitIntExt()
2707   bool ImmIsSO = (Shift != ARM_AM::no_shift);  in ARMEmitIntExt()