Lines Matching refs:DefAlign
3869 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3896 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) in getVLDMDefCycle()
3910 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3929 if ((RegNo % 2) || DefAlign < 8) in getLDMDefCycle()
4013 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
4038 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
4059 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
4179 const MCInstrDesc &DefMCID, unsigned DefAlign) { in adjustDefLatency() argument
4239 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) { in adjustDefLatency()
4425 unsigned DefAlign = DefMI.hasOneMemOperand() in getOperandLatencyImpl() local
4433 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID, in getOperandLatencyImpl()
4443 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); in getOperandLatencyImpl()
4475 unsigned DefAlign = !DefMN->memoperands_empty() in getOperandLatency() local
4482 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, in getOperandLatency()
4542 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) in getOperandLatency()
4771 unsigned DefAlign = in getInstrLatency() local
4773 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign); in getInstrLatency()