1101 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()  function in ARMBaseInstrInfo
1173           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1174           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
1184           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1185           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
1235           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1236           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1237           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1267           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1268           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1269           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1270                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
1287         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1288         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1289         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1290         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
1291         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);  in storeRegToStackSlot()
1292         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);  in storeRegToStackSlot()
1293         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);  in storeRegToStackSlot()
1294               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);  in storeRegToStackSlot()
1427         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1428         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1438         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1439         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1485         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1486         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1487         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1514          MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1515          MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1516          MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1517          MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1535       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1536       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1537       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1538       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1539       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1540       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1541       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1542       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()