113 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)  in ARMBaseInstrInfo()  function in ARMBaseInstrInfo
127 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,  in CreateTargetHazardRecognizer()
140 ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(  in CreateTargetMIHazardRecognizer()
162 ScheduleHazardRecognizer *ARMBaseInstrInfo::
177 ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,  in convertToThreeAddress()
353 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,  in analyzeBranch()
469 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
496 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
548 bool ARMBaseInstrInfo::
558 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {  in isPredicated()
574 std::string ARMBaseInstrInfo::createMIROperandComment(  in createMIROperandComment()
599 bool ARMBaseInstrInfo::PredicateInstruction(  in PredicateInstruction()
632 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,  in SubsumesPredicate()
658 bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,  in ClobbersPredicate()
682 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {  in isCPSRDefined()
714     return !ARMBaseInstrInfo::isCPSRDefined(*MI);  in isEligibleForITBlock()
721 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {  in isPredicable()
775 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
813 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {  in getInstBundleLength()
824 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,  in copyFromCPSR()
844 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,  in copyToCPSR()
888 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
1055 ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {  in isCopyInstrImpl()
1071 ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,  in describeLoadedValue()
1101 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()
1112 void ARMBaseInstrInfo::
1303 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
1355 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,  in isStoreToStackSlotPostFE()
1368 void ARMBaseInstrInfo::
1553 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
1611 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,  in isLoadFromStackSlotPostFE()
1626 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {  in expandMEMCPY()
1629   const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();  in expandMEMCPY()
1680 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
1803 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,  in reMaterialize()
1831 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,  in duplicate()
1855 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,  in produceSameValue()
1943 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,  in areLoadsFromSameBasePtr()
2024 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,  in shouldScheduleLoadsNear()
2054 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
2104 bool ARMBaseInstrInfo::
2130 bool ARMBaseInstrInfo::
2195 ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF,  in extraSizeToPredicateInstructions()
2209 ARMBaseInstrInfo::predictBranchSizeForIfCvt(MachineInstr &MI) const {  in predictBranchSizeForIfCvt()
2232 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,  in isProfitableToUnpredicate()
2265 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,  in commuteInstructionImpl()
2294 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,  in canFoldIntoMOVCC()
2328 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,  in analyzeSelect()
2350 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,  in optimizeSelect()
2482                                    const ARMBaseInstrInfo &TII,  in emitARMRegPlusImmediate()
2642                                 const ARMBaseInstrInfo &TII) {  in rewriteARMFrameIndex()
2797 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,  in analyzeCompare()
3005 bool ARMBaseInstrInfo::optimizeCompareInstr(  in optimizeCompareInstr()
3284 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {  in shouldSink()
3302 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
3698 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {  in getNumLDMAddresses()
3752 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()
3866 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()
3907 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()
3942 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()
3982 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()
4011 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4355 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4391 int ARMBaseInstrInfo::getOperandLatencyImpl(  in getOperandLatencyImpl()
4452 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4710 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {  in getPredicationCost()
4729 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4780 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4798 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,  in hasHighOperandLatency()
4819 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,  in hasLowDefLatency()
4835 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
4906 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,  in expandLoadStackGuardBase()
4984 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,  in isFpMLxInstruction()
5020 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {  in getExecutionDomain()
5110 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,  in setExecutionDomain()
5318 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(  in getPartialRegUpdateClearance()
5379 void ARMBaseInstrInfo::breakPartialRegDependency(  in breakPartialRegDependency()
5413 bool ARMBaseInstrInfo::hasNOP() const {  in hasNOP()
5417 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {  in isSwiftFastImmShift()
5431 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(  in getRegSequenceLikeInputs()
5458 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(  in getExtractSubregLikeInputs()
5481 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(  in getInsertSubregLikeInputs()
5509 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
5515 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
5524 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {  in getSerializableBitmaskMachineOperandTargetFlags()
5537 Optional<RegImmPair> ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,  in isAddImmediate()
5799 ARMBaseInstrInfo::findRegisterToSaveLRTo(outliner::Candidate &C) const {  in findRegisterToSaveLRTo()
5850 outliner::OutlinedFunction ARMBaseInstrInfo::getOutliningCandidateInfo(  in getOutliningCandidateInfo()
6069 bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI,  in checkAndUpdateStackOffset()
6172 void ARMBaseInstrInfo::mergeOutliningCandidateAttributes(  in mergeOutliningCandidateAttributes()
6184 bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom(  in isFunctionSafeToOutlineFrom()
6207 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,  in isMBBSafeToOutlineFrom()
6256 ARMBaseInstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  in getOutliningType()
6429 void ARMBaseInstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {  in fixupPostOutline()
6435 void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,  in saveLROnStack()
6496 void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,  in emitCFIForLRSaveToReg()
6511 void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,  in restoreLRFromStack()
6571 void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(  in emitCFIForLRRestoreFromReg()
6584 void ARMBaseInstrInfo::buildOutlinedFrame(  in buildOutlinedFrame()
6660 MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(  in insertOutlinedCall()
6724 bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(  in shouldOutlineFromFunctionByDefault()
6729 bool ARMBaseInstrInfo::isReallyTriviallyReMaterializable(  in isReallyTriviallyReMaterializable()
6818 ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {  in analyzeLoopForPipelining()