Lines Matching refs:asmstr
96 class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
102 let AsmString = asmstr;
120 class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
121 : InstARC<0, outs, ins, asmstr, pattern> {
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
157 InstARC<4, outs, ins, asmstr, pattern> {
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
167 F32_BR<major, outs, ins, b16, asmstr, pattern> {
175 class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
177 F32_BR<major, outs, ins, b16, asmstr, pattern> {
185 class F32_BR0_COND<dag outs, dag ins, string asmstr, list<dag> pat> :
186 F32_BR_COND<0b00000, outs, ins, 0, asmstr, pat> {
193 class F32_BR0_UCOND_FAR<dag outs, dag ins, string asmstr, list<dag> pat> :
194 F32_BR_UCOND_FAR<0b00000, outs, ins, 1, asmstr, pat> {
201 class F32_BR1_BL_UCOND_FAR<dag outs, dag ins, string asmstr, list<dag> pat> :
202 F32_BR_UCOND_FAR<0b00001, outs, ins, 0, asmstr, pat> {
209 class F32_BR1_BL_COND<dag outs, dag ins, string asmstr, list<dag> pat> :
210 F32_BR_COND<0b00001, outs, ins, 0, asmstr, pat> {
219 class F32_BR1_BCC<dag outs, dag ins, string asmstr, bit IsU6,
221 InstARC<4, outs, ins, asmstr, pattern> {
248 string asmstr, list<dag> pattern> :
249 InstARC<4, outs, ins, asmstr, pattern> {
271 string asmstr, list<dag> pattern> :
272 InstARC<4, outs, ins, asmstr, pattern> {
292 string asmstr, list<dag> pattern> :
293 InstARC<4, outs, ins, asmstr, pattern> {
314 string asmstr, list<dag> pattern> :
315 InstARC<4, outs, ins, asmstr, pattern> {
335 string asmstr, list<dag> pattern> :
336 InstARC<4, outs, ins, asmstr, pattern> {
361 string asmstr, list<dag> pattern> :
362 InstARC<4, outs, ins, asmstr, pattern> {
383 string asmstr, list<dag> pattern> :
384 InstARC<4, outs, ins, asmstr, pattern> {
403 string asmstr, list<dag> pattern> :
404 InstARC<4, outs, ins, asmstr, pattern> {
425 string asmstr, list<dag> pattern> :
426 InstARC<4, outs, ins, asmstr, pattern> {
446 string asmstr, list<dag> pattern> :
447 InstARC<8, outs, ins, asmstr, pattern> {
483 string asmstr, list<dag> pattern> :
484 InstARC<4, outs, ins, asmstr, pattern> {
504 string asmstr, list<dag> pattern> :
505 F32_LD_RS9<x, aa, di, zz, outs, ins, asmstr, pattern> {
519 string asmstr, list<dag> pattern> :
520 InstARC<8, outs, ins, asmstr, pattern> {
544 string asmstr, list<dag> pattern> :
545 InstARC<8, outs, ins, asmstr, pattern> {
574 string asmstr, list<dag> pattern> :
575 InstARC<4, outs, ins, asmstr, pattern> {
595 string asmstr, list<dag> pattern> :
596 F32_ST_RS9<aa, di, zz, outs, ins, asmstr, pattern> {
609 string asmstr, list<dag> pattern> :
610 InstARC<8, outs, ins, asmstr, pattern> {
634 string asmstr> :
635 InstARC<2, outs, ins, asmstr, []> {
646 class F16_LD_ADD_SUB<dag outs, dag ins, string asmstr> :
647 InstARC<2, outs, ins, asmstr, []> {
654 class F16_LD_SUB<bit i, string asmstr> :
656 asmstr> {
681 class F16_LD_ST_1<dag outs, dag ins, string asmstr> :
682 InstARC<2, outs, ins, asmstr, []> {
687 class F16_LD_ST_s11<bit i, string asmstr> :
688 F16_LD_ST_1<(outs), (ins immS<11>:$s11), asmstr> {
713 class F16_JLI_EI<bit i, string asmstr> :
715 !strconcat(asmstr, "\t$u10"), []> {
725 class F16_LD_ADD_RR<bits<2> i, string asmstr> :
727 asmstr, []> {
741 class F16_GP_LD_ADD<bits<2> i, dag ins, string asmstr> :
742 InstARC<2, (outs), ins, asmstr, []> {
751 class F16_ADD_IMM<bits<2> i, string asmstr> :
753 !strconcat(asmstr, "\t$c, $b, $u3"), []> {
769 class F16_OP_HREG<bits<3> i, dag outs, dag ins, string asmstr> :
770 InstARC<2, outs, ins, asmstr, []> {
782 class F16_OP_HREG30<bits<3> i, dag outs, dag ins, string asmstr> :
783 F16_OP_HREG<i, outs, ins, asmstr> {
790 class F16_OP_HREG_LIMM<bits<3> i, dag outs, dag ins, string asmstr> :
791 F16_OP_HREG30<i, outs, ins, asmstr> {
799 class F16_GEN_DOP_BASE<bits<5> i, dag outs, dag ins, string asmstr> :
800 InstARC<2, outs, ins, asmstr, []> {
810 class F16_GEN_DOP<bits<5> i, string asmstr> :
812 !strconcat(asmstr, "\t$b, $b, $c")>;
814 class F16_GEN_DOP_NODST<bits<5> i, string asmstr> :
816 !strconcat(asmstr, "\t$b, $c")>;
818 class F16_GEN_DOP_SINGLESRC<bits<5> i, string asmstr> :
820 !strconcat(asmstr, "\t$b, $c")>;
822 class F16_GEN_SOP_BASE<bits<3> i, dag outs, dag ins, string asmstr> :
823 F16_GEN_DOP_BASE<0b00000, outs, ins, asmstr> {
828 class F16_GEN_SOP<bits<3> i, string asmstr> :
829 F16_GEN_SOP_BASE<i, (outs), (ins GPR32:$b), asmstr>;
831 class F16_GEN_ZOP<bits<3> i, string asmstr> :
832 F16_GEN_SOP_BASE<0b111, (outs), (ins), asmstr> {
838 class F16_LD_ST_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
839 InstARC<2, outs, ins, !strconcat(asmstr, "\t$c, [$b, $off]"), []> {
848 class F16_LD_ST_WORD_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
849 F16_LD_ST_OFF<opc, outs, ins, asmstr> {
856 class F16_LD_ST_HALF_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
857 F16_LD_ST_OFF<opc, outs, ins, asmstr> {
864 class F16_LD_ST_BYTE_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
865 F16_LD_ST_OFF<opc, outs, ins, asmstr> {
874 class F16_SH_SUB_BIT<bits<3> i, string asmstr> :
875 InstARC<2, (outs), (ins GPR32:$b, immU<5>:$u5), asmstr, []> {
886 class F16_SH_SUB_BIT_DST<bits<3> i, string asmstr> :
887 F16_SH_SUB_BIT<i, !strconcat(asmstr, "\t$b, $b, $u5")>;
893 dag outs, dag ins, string asmstr> :
894 InstARC<2, outs, ins, asmstr, []> {
906 dag outs, dag ins, string asmstr> :
907 F16_SP_OPS<i, outs, ins, asmstr> {
950 class F16_OP_IMM<bits<5> opc, dag outs, dag ins, string asmstr> :
951 InstARC<2, outs, ins, asmstr, []> {
958 class F16_OP_U7<bit i, string asmstr> :
959 F16_OP_IMM<0b11100, (outs GPR32:$b), (ins immU<7>:$u7), asmstr> {
1007 class F16_BCC_REG<bit i, string asmstr> :
1009 !strconcat(asmstr, "\t$b, 0, $s8"), []> {
1022 class F16_BCC<bits<2> i, dag ins, string asmstr> :
1023 InstARC<2, (outs), ins, asmstr, []> {
1029 class F16_BCC_s10<bits<2> i, string asmstr> :
1031 !strconcat(asmstr, "\t$s")> {
1038 class F16_BCC_s7<bits<3> i, string asmstr> :
1040 !strconcat(asmstr, "\t$s")> {