Lines Matching refs:ps
57 class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
58 : InstSI<ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands> {
66 let LGKM_CNT = ps.LGKM_CNT;
67 let SMRD = ps.SMRD;
68 let mayStore = ps.mayStore;
69 let mayLoad = ps.mayLoad;
70 let hasSideEffects = ps.hasSideEffects;
71 let UseNamedOperandTable = ps.UseNamedOperandTable;
72 let SchedRW = ps.SchedRW;
73 let SubtargetPredicate = ps.SubtargetPredicate;
74 let AsmMatchConverter = ps.AsmMatchConverter;
75 let IsAtomicRet = ps.IsAtomicRet;
76 let IsAtomicNoRet = ps.IsAtomicNoRet;
78 let TSFlags = ps.TSFlags;
80 bit is_buffer = ps.is_buffer;
481 class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
482 : SM_Real<ps>
483 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
489 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
490 let Inst{8} = ps.has_offset;
491 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
492 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
497 multiclass SM_Real_Loads_si<bits<5> op, string ps,
498 SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
499 SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
530 class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
531 : SM_Real<ps>
532 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
538 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
539 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
546 !if(ps.has_offset, ps.has_soffset, !if(ps.has_soffset, 0, ?)),
550 let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
555 let Inst{17} = ps.has_offset;
564 let Offset{6-0} = !if(ps.has_offset, offset{6-0},
565 !if(ps.has_soffset, soffset{6-0}, ?));
566 let Offset{20-7} = !if(ps.has_offset, offset{20-7}, ?);
570 let Inst{63-57} = !if(!and(IsGFX9SpecificEncoding, ps.has_soffset),
574 class SMEM_Real_Load_vi<bits<8> op, string ps, OffsetMode offsets>
575 : SMEM_Real_vi<op, !cast<SM_Pseudo>(ps # offsets.Variant)> {
576 RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps # offsets.Variant).BaseClass;
591 multiclass SM_Real_Loads_vi<bits<8> op, string ps> {
592 def _IMM_vi : SMEM_Real_Load_vi <op, ps, IMM_Offset>;
593 def _SGPR_vi : SMEM_Real_Load_vi <op, ps, SGPR_Offset>;
594 def _SGPR_alt_gfx9 : SMEM_Real_Load_vi <op, ps, SGPR_Offset>,
597 def _SGPR_IMM_gfx9 : SMEM_Real_Load_vi <op, ps, SGPR_IMM_Offset>;
600 class SMEM_Real_Store_Base_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
605 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
608 class SMEM_Real_Store_vi <bits<8> op, string ps, dag offsets>
609 : SMEM_Real_Store_Base_vi <op, !cast<SM_Pseudo>(ps)> {
610 RegisterClass SrcClass = !cast<SM_Store_Pseudo>(ps).SrcClass;
611 RegisterClass BaseClass = !cast<SM_Store_Pseudo>(ps).BaseClass;
616 multiclass SM_Real_Stores_vi<bits<8> op, string ps> {
617 def _IMM_vi : SMEM_Real_Store_vi <op, ps#_IMM, (ins smem_offset:$offset)>;
618 def _SGPR_vi : SMEM_Real_Store_vi <op, ps#_SGPR, (ins SReg_32:$soffset)>;
619 def _SGPR_alt_gfx9 : SMEM_Real_Store_vi <op, ps#"_SGPR",
624 op, ps#"_SGPR_IMM", (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
627 multiclass SM_Real_Probe_vi<bits<8> op, string ps> {
628 def _IMM_vi : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
629 def _SGPR_vi : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
631 : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>,
635 : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR_IMM)>;
680 class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
681 : SMEM_Real_vi <op, ps>,
682 AtomicNoRet <!subst("_RTN","",NAME), ps.glc> {
686 let Constraints = ps.Constraints;
687 let DisableEncoding = ps.DisableEncoding;
689 let cpol{CPolBit.GLC} = ps.glc;
690 let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
693 multiclass SM_Real_Atomics_vi<bits<8> op, string ps> {
694 def _IMM_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_IMM)>;
695 def _SGPR_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>;
697 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>,
701 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM)>;
702 def _IMM_RTN_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_IMM_RTN)>;
703 def _SGPR_RTN_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>;
705 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>,
709 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM_RTN)>;
768 multiclass SM_Real_Discard_vi<bits<8> op, string ps> {
769 def _IMM_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_IMM)>;
770 def _SGPR_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>;
771 def _SGPR_alt_gfx9 : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>,
774 def _SGPR_IMM_gfx9 : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR_IMM)>;
789 class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
790 SM_Real<ps>,
795 let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol);
817 class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
818 : SM_Real<ps>
819 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
825 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
826 let Inst{8} = ps.has_offset;
827 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
828 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
982 class SMEM_Real_10Plus_common<bits<8> op, SM_Pseudo ps, string opName,
984 SM_Real<ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>, Enc64 {
985 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
986 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
991 let Inst{52-32} = !if(ps.has_offset, offset{20-0}, !if(ps.has_soffset, 0, ?));
992 let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
993 !if(ps.has_offset, sgpr_null.HWEncoding{6-0}, ?));
996 class SMEM_Real_gfx10<bits<8> op, SM_Pseudo ps>
997 : SMEM_Real_10Plus_common<op, ps, ps.Mnemonic, SIEncodingFamily.GFX10,
1001 let Inst{14} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ?);
1002 let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
1005 class SMEM_Real_Load_gfx10<bits<8> op, string ps, OffsetMode offsets>
1006 : SMEM_Real_gfx10<op, !cast<SM_Pseudo>(ps # offsets.Variant)> {
1007 RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps # offsets.Variant).BaseClass;
1011 multiclass SM_Real_Loads_gfx10<bits<8> op, string ps> {
1012 def _IMM_gfx10 : SMEM_Real_Load_gfx10<op, ps, IMM_Offset>;
1013 def _SGPR_gfx10 : SMEM_Real_Load_gfx10<op, ps, SGPR_Offset>;
1014 def _SGPR_IMM_gfx10 : SMEM_Real_Load_gfx10<op, ps, SGPR_IMM_Offset>;
1017 class SMEM_Real_Store_gfx10<bits<8> op, SM_Pseudo ps> : SMEM_Real_gfx10<op, ps> {
1021 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
1024 multiclass SM_Real_Stores_gfx10<bits<8> op, string ps,
1025 SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
1026 SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
1035 def _SGPR_IMM_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Store_Pseudo>(ps#_SGPR_IMM)> {
1083 multiclass SM_Real_Probe_gfx10<bits<8> op, string ps> {
1084 def _IMM_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
1085 def _SGPR_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
1087 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR_IMM)>;
1093 class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
1094 : SMEM_Real_gfx10 <op, ps>,
1095 AtomicNoRet <!subst("_RTN","",NAME), ps.glc> {
1099 let Constraints = ps.Constraints;
1100 let DisableEncoding = ps.DisableEncoding;
1102 let cpol{CPolBit.GLC} = ps.glc;
1104 let Inst{14} = !if(ps.has_dlc, cpol{CPolBit.DLC}, 0);
1105 let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
1108 multiclass SM_Real_Atomics_gfx10<bits<8> op, string ps> {
1109 def _IMM_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_IMM)>;
1110 def _SGPR_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>;
1111 def _SGPR_IMM_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM)>;
1112 def _IMM_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_IMM_RTN)>;
1113 def _SGPR_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>;
1114 def _SGPR_IMM_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM_RTN)>;
1175 multiclass SM_Real_Discard_gfx10<bits<8> op, string ps> {
1176 def _IMM_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
1177 def _SGPR_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
1178 def _SGPR_IMM_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR_IMM)>;
1199 class SMEM_Real_gfx11<bits<8> op, SM_Pseudo ps, string opName = ps.Mnemonic> :
1200 SMEM_Real_10Plus_common<op, ps, opName, SIEncodingFamily.GFX11,
1204 let Inst{13} = !if(ps.has_dlc, cpol{CPolBit.DLC}, 0);
1205 let Inst{14} = !if(ps.has_glc, cpol{CPolBit.GLC}, 0);
1208 class SMEM_Real_Load_gfx11<bits<8> op, string ps, string opName, OffsetMode offsets> :
1209 SMEM_Real_gfx11<op, !cast<SM_Pseudo>(ps # offsets.Variant), opName> {
1210 RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps # offsets.Variant).BaseClass;
1214 multiclass SM_Real_Loads_gfx11<bits<8> op, string ps, string opName> {
1215 def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps, opName, IMM_Offset>;
1216 def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps, opName, SGPR_Offset>;
1217 def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps, opName, SGPR_IMM_Offset>;
1218 def : MnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName>,
1237 class SMEM_Real_Store_gfx11 <bits<8> op, SM_Pseudo ps> : SMEM_Real_gfx11<op, ps> {
1242 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
1245 multiclass SM_Real_Probe_gfx11<bits<8> op, string ps> {
1246 def _IMM_gfx11 : SMEM_Real_Store_gfx11 <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
1247 def _SGPR_gfx11 : SMEM_Real_Store_gfx11 <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
1249 : SMEM_Real_Store_gfx11 <op, !cast<SM_Probe_Pseudo>(ps#_SGPR_IMM)>;