Lines Matching refs:opName
31 class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
33 SIMCInstr<opName, SIEncodingFamily.NONE> {
45 string Mnemonic = opName;
57 class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
58 : InstSI<ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands> {
105 class SM_Probe_Pseudo <string opName, string variant, RegisterClass baseClass,
108 : SM_Pseudo<opName, (outs),
119 let PseudoInstr = opName # variant;
122 class SM_Load_Pseudo <string opName, RegisterClass baseClass,
124 : SM_Pseudo<opName, (outs dstClass:$sdst),
134 let PseudoInstr = opName # offsets.Variant;
137 class SM_Store_Pseudo <string opName, RegisterClass baseClass,
139 : SM_Pseudo<opName, (outs), ins, asmOps, []> {
149 class SM_Discard_Pseudo <string opName, string variant, dag offsets,
151 : SM_Pseudo<opName, (outs), !con((ins SReg_64:$sbase), offsets),
161 let PseudoInstr = opName # variant;
164 multiclass SM_Pseudo_Loads<string opName,
167 def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
168 def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
169 def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
172 multiclass SM_Pseudo_Stores<string opName,
175 def _IMM : SM_Store_Pseudo <opName, baseClass, srcClass,
179 let PseudoInstr = opName # "_IMM";
182 def _SGPR : SM_Store_Pseudo <opName, baseClass, srcClass,
186 let PseudoInstr = opName # "_SGPR";
189 def _SGPR_IMM : SM_Store_Pseudo <opName, baseClass, srcClass,
195 let PseudoInstr = opName # "_SGPR_IMM";
199 multiclass SM_Pseudo_Discards<string opName> {
200 def _IMM : SM_Discard_Pseudo <opName, "_IMM",
202 def _SGPR : SM_Discard_Pseudo <opName, "_SGPR",
204 def _SGPR_IMM : SM_Discard_Pseudo <opName, "_SGPR_IMM",
208 class SM_Time_Pseudo<string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
209 opName, (outs SReg_64_XEXEC:$sdst), (ins),
218 class SM_Inval_Pseudo <string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
219 opName, (outs), (ins), "", [(node)]> {
227 multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> {
228 def _IMM : SM_Probe_Pseudo <opName, "_IMM", baseClass,
230 def _SGPR : SM_Probe_Pseudo <opName, "_SGPR", baseClass,
232 def _SGPR_IMM : SM_Probe_Pseudo <opName, "_SGPR_IMM", baseClass,
236 class SM_WaveId_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
237 opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
249 class SM_Atomic_Pseudo <string opName,
251 : SM_Pseudo<opName, outs, ins, asmOps, []> {
272 class SM_Pseudo_Atomic<string opName,
278 opName # offsets.Variant # !if(isRet, "_RTN", ""),
280 SM_Atomic_Pseudo<opName,
296 multiclass SM_Pseudo_Atomics<string opName,
299 def _IMM : SM_Pseudo_Atomic <opName, baseClass, dataClass, IMM_Offset, 0>;
300 def _SGPR : SM_Pseudo_Atomic <opName, baseClass, dataClass, SGPR_Offset, 0>;
301 def _SGPR_IMM : SM_Pseudo_Atomic <opName, baseClass, dataClass, SGPR_IMM_Offset, 0>;
302 def _IMM_RTN : SM_Pseudo_Atomic <opName, baseClass, dataClass, IMM_Offset, 1>;
303 def _SGPR_RTN : SM_Pseudo_Atomic <opName, baseClass, dataClass, SGPR_Offset, 1>;
304 def _SGPR_IMM_RTN : SM_Pseudo_Atomic <opName, baseClass, dataClass, SGPR_IMM_Offset, 1>;
982 class SMEM_Real_10Plus_common<bits<8> op, SM_Pseudo ps, string opName,
984 SM_Real<ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>, Enc64 {
1199 class SMEM_Real_gfx11<bits<8> op, SM_Pseudo ps, string opName = ps.Mnemonic> :
1200 SMEM_Real_10Plus_common<op, ps, opName, SIEncodingFamily.GFX11,
1208 class SMEM_Real_Load_gfx11<bits<8> op, string ps, string opName, OffsetMode offsets> :
1209 SMEM_Real_gfx11<op, !cast<SM_Pseudo>(ps # offsets.Variant), opName> {
1214 multiclass SM_Real_Loads_gfx11<bits<8> op, string ps, string opName> {
1215 def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps, opName, IMM_Offset>;
1216 def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps, opName, SGPR_Offset>;
1217 def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps, opName, SGPR_IMM_Offset>;
1218 def : MnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName>,