110     unsigned Width;  member
683   Width = getOpcodeWidth(*I, *LSO.TII);  in setMI()
901     if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0)  in offsetsCanBeCombined()
912     return (EltOffset0 + CI.Width == EltOffset1 ||  in offsetsCanBeCombined()
913             EltOffset1 + Paired.Width == EltOffset0) &&  in offsetsCanBeCombined()
979   const unsigned Width = (CI.Width + Paired.Width);  in widthsFit()  local
982     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
984     switch (Width) {  in widthsFit()
1419       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1491       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
1600   const unsigned Width = CI.Width + Paired.Width;  in getNewOpcode()  local
1607                                   Width);  in getNewOpcode()
1611                                   Width);  in getNewOpcode()
1616     switch (Width) {  in getNewOpcode()
1627     switch (Width) {  in getNewOpcode()
1638     switch (Width) {  in getNewOpcode()
1649     switch (Width) {  in getNewOpcode()
1660     switch (Width) {  in getNewOpcode()
1671     switch (Width) {  in getNewOpcode()
1682     switch (Width) {  in getNewOpcode()
1693     assert((countPopulation(CI.DMask | Paired.DMask) == Width) &&  in getNewOpcode()
1695     return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);  in getNewOpcode()
1703                                    CI.Width + Paired.Width)) &&  in getSubRegIdxs()
1717   assert(CI.Width >= 1 && CI.Width <= 4);  in getSubRegIdxs()
1718   assert(Paired.Width >= 1 && Paired.Width <= 4);  in getSubRegIdxs()
1721     Idx1 = Idxs[0][Paired.Width - 1];  in getSubRegIdxs()
1722     Idx0 = Idxs[Paired.Width][CI.Width - 1];  in getSubRegIdxs()
1724     Idx0 = Idxs[0][CI.Width - 1];  in getSubRegIdxs()
1725     Idx1 = Idxs[CI.Width][Paired.Width - 1];  in getSubRegIdxs()
1735     switch (CI.Width + Paired.Width) {  in getTargetRegisterClass()
1749   unsigned BitWidth = 32 * (CI.Width + Paired.Width);  in getTargetRegisterClass()
2304       OptimizeListAgain |= CI.Width + Paired.Width < 8;  in optimizeInstsWithSameBaseAddr()
2308       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2312       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2316       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2320       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2324       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2330       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2336       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()