Lines Matching refs:src0
71 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
76 (ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
78 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
81 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
110 (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
119 (ins VSrc_b64:$src0)> {
135 (ins i64imm:$src0)> {
146 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
150 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
154 // the instruction that defines $src0 (which is run in Whole Wave Mode) doesn't
157 def STRICT_WWM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
158 def STRICT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
163 def ENTER_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
171 def EXIT_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
177 def ENTER_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
185 def EXIT_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
199 (ins VGPR_32:$src0),
200 [(set f16:$vdst, (SIfptrunc_round_upward f32:$src0))]>;
203 (ins VGPR_32:$src0),
204 [(set f16:$vdst, (SIfptrunc_round_downward f32:$src0))]>;
223 (outs VReg_64:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
224 [(set VReg_64:$vdst, (getDivergentFrag<add>.ret i64:$src0, i64:$src1))]
228 (outs VReg_64:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
229 [(set VReg_64:$vdst, (getDivergentFrag<sub>.ret i64:$src0, i64:$src1))]
235 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
236 [(set SReg_64:$sdst, (UniformBinFrag<add> i64:$src0, i64:$src1))]
240 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
241 [(set SReg_64:$sdst, (UniformBinFrag<sub> i64:$src0, i64:$src1))]
245 (outs SReg_64:$vdst, VOPDstS64orS32:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
249 (outs SReg_64:$vdst, VOPDstS64orS32:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
253 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_i1:$scc_in)
257 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_i1:$scc_in)
261 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1)
265 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1)
426 defm SI_KILL_F32_COND_IMM : PseudoInstKill <(ins VSrc_b32:$src0, i32imm:$src1, i32imm:$cond)>;
523 (outs), (ins SSrc_b64:$src0, unknown:$callee),
524 [(AMDGPUcall i64:$src0, tglobaladdr:$callee)]> {
534 (AMDGPUcall i64:$src0, (i64 0)),
535 (SI_CALL_ISEL $src0, (i64 0))
541 (outs SReg_64:$dst), (ins SSrc_b64:$src0, unknown:$callee)> {
553 (ins SReg_64:$src0, unknown:$callee, i32imm:$fpdiff),
554 [(AMDGPUtc_return i64:$src0, tglobaladdr:$callee, i32:$fpdiff)]> {
569 (AMDGPUtc_return i64:$src0, (i64 0), (i32 timm:$fpdiff)),
570 (SI_TCRETURN SReg_64:$src0, (i64 0), i32imm:$fpdiff)
906 (f32 (f16_to_fp i32:$src0)),
907 (V_CVT_F32_F16_e64 SRCMODS.NONE, $src0)
911 (f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))),
912 (V_CVT_F32_F16_e64 SRCMODS.ABS, $src0)
916 (f32 (f16_to_fp (i32 (srl_oneuse (and_oneuse i32:$src0, 0x7fff0000), (i32 16))))),
917 (V_CVT_F32_F16_e64 SRCMODS.ABS, (i32 (V_LSHRREV_B32_e64 (i32 16), i32:$src0)))
921 (f32 (f16_to_fp (or_oneuse i32:$src0, 0x8000))),
922 (V_CVT_F32_F16_e64 SRCMODS.NEG_ABS, $src0)
926 (f32 (f16_to_fp (xor_oneuse i32:$src0, 0x8000))),
927 (V_CVT_F32_F16_e64 SRCMODS.NEG, $src0)
937 (i32 (AMDGPUfp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
938 (V_CVT_F16_F32_e64 $src0_modifiers, f32:$src0)
968 : GCNPat <(vt (node (vt (VOP3NoMods vt:$src0)),
971 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
987 (f32 (fadd (AMDGPUfmul_legacy (VOP3NoMods f32:$src0),
990 (V_MAC_LEGACY_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
998 (f32 (int_amdgcn_fma_legacy (VOP3NoMods f32:$src0),
1001 (V_FMAC_LEGACY_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
1013 (Ty (mad_opr (Ty (VOP3Mods Ty:$src0, i32:$src0_mod)),
1016 (inst $src0_mod, $src0, $src1_mod, $src1,
1025 (f32 (fadd (AMDGPUfmul_legacy (VOP3Mods f32:$src0, i32:$src0_mod),
1028 (V_MAD_LEGACY_F32_e64 $src0_mod, $src0, $src1_mod, $src1,
1036 (vt (select i1:$src0, (VOP3Mods vt:$src1, i32:$src1_mods),
1039 FP32InputMods:$src1_mods, VSrc_b32:$src1, SSrc_i1:$src0)
1043 (vt (select i1:$src0, vt:$src1, vt:$src2)),
1044 (V_CNDMASK_B32_e64 0, VSrc_b32:$src2, 0, VSrc_b32:$src1, SSrc_i1:$src0)
1498 (vt (AMDGPUclamp (VOP3Mods vt:$src0, i32:$src0_modifiers))),
1499 (inst i32:$src0_modifiers, vt:$src0,
1500 i32:$src0_modifiers, vt:$src0, DSTCLAMP.ENABLE, DSTOMOD.NONE)
1509 (v2f16 (AMDGPUclamp (VOP3PMods v2f16:$src0, i32:$src0_modifiers))),
1510 (V_PK_MAX_F16 $src0_modifiers, $src0,
1511 $src0_modifiers, $src0, DSTCLAMP.ENABLE)
1727 (fcopysign f16:$src0, f16:$src1),
1728 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0, $src1)
1732 (fcopysign f32:$src0, f16:$src1),
1733 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0,
1738 (fcopysign f64:$src0, f16:$src1),
1740 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
1741 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), (i32 (EXTRACT_SUBREG $src0, sub1)),
1746 (fcopysign f16:$src0, f32:$src1),
1747 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0,
1752 (fcopysign f16:$src0, f64:$src1),
1753 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0,
1846 (f32 (fpow (VOP3Mods f32:$src0, i32:$src0_mods), (VOP3Mods f32:$src1, i32:$src1_mods))),
1847 …E, (V_MUL_LEGACY_F32_e64 $src1_mods, $src1, SRCMODS.NONE, (V_LOG_F32_e64 $src0_mods, $src0), 0, 0))
1851 (i32 (sext i1:$src0)),
1852 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
1853 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src0)
1857 (i32 (ext i1:$src0)),
1858 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
1859 /*src1mod*/(i32 0), /*src1*/(i32 1), $src0)
1868 (AMDGPUurecip i32:$src0),
1871 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
1939 (fcopysign f32:$src0, f32:$src1),
1940 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0, $src1)
1944 (fcopysign f32:$src0, f64:$src1),
1945 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0,
1950 (fcopysign f64:$src0, f64:$src1),
1952 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
1954 (i32 (EXTRACT_SUBREG SReg_64:$src0, sub1)),
1959 (fcopysign f64:$src0, f32:$src1),
1961 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
1963 (i32 (EXTRACT_SUBREG SReg_64:$src0, sub1)),
1969 def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
1970 (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
1971 (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
1973 def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
1974 (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
1975 (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
2012 (add (sub_oneuse (umax i32:$src0, i32:$src1),
2013 (umin i32:$src0, i32:$src1)),
2015 (V_SAD_U32_e64 $src0, $src1, $src2, (i1 0))
2019 (add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
2020 (sub i32:$src0, i32:$src1),
2021 (sub i32:$src1, i32:$src0)),
2023 (V_SAD_U32_e64 $src0, $src1, $src2, (i1 0))
2128 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2154 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2156 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2161 (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
2162 (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))
2181 (i1 (and i1:$src0, i1:$src1)),
2182 (S_AND_B64 $src0, $src1)
2186 (i1 (or i1:$src0, i1:$src1)),
2187 (S_OR_B64 $src0, $src1)
2191 (i1 (xor i1:$src0, i1:$src1)),
2192 (S_XOR_B64 $src0, $src1)
2196 (i1 (add i1:$src0, i1:$src1)),
2197 (S_XOR_B64 $src0, $src1)
2201 (i1 (sub i1:$src0, i1:$src1)),
2202 (S_XOR_B64 $src0, $src1)
2207 (i1 (add i1:$src0, (i1 -1))),
2208 (S_NOT_B64 $src0)
2212 (i1 (sub i1:$src0, (i1 -1))),
2213 (S_NOT_B64 $src0)
2220 (i1 (and i1:$src0, i1:$src1)),
2221 (S_AND_B32 $src0, $src1)
2225 (i1 (or i1:$src0, i1:$src1)),
2226 (S_OR_B32 $src0, $src1)
2230 (i1 (xor i1:$src0, i1:$src1)),
2231 (S_XOR_B32 $src0, $src1)
2235 (i1 (add i1:$src0, i1:$src1)),
2236 (S_XOR_B32 $src0, $src1)
2240 (i1 (sub i1:$src0, i1:$src1)),
2241 (S_XOR_B32 $src0, $src1)
2246 (i1 (add i1:$src0, (i1 -1))),
2247 (S_NOT_B32 $src0)
2251 (i1 (sub i1:$src0, (i1 -1))),
2252 (S_NOT_B32 $src0)
2258 (i32 (DivergentBinFrag<xor> i32:$src0, (i32 -1))),
2259 (V_NOT_B32_e32 $src0)
2263 (i64 (DivergentBinFrag<xor> i64:$src0, (i64 -1))),
2265 (V_NOT_B32_e32 (i32 (EXTRACT_SUBREG i64:$src0, sub0))), sub0,
2266 (V_NOT_B32_e32 (i32 (EXTRACT_SUBREG i64:$src0, sub1))), sub1
2273 V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2281 V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2288 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2295 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2302 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2309 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2455 // My reading of the manual suggests we should be using src0 for the
2594 (fma (f32 (VOP3NoMods f32:$src0)),
2597 (V_FMAC_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
2606 (fma (f16 (VOP3NoMods f32:$src0)),
2609 (V_FMAC_F16_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
2617 (fma (f64 (VOP3NoMods f64:$src0)),
2620 (V_FMAC_F64_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
2658 (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 undef))),
2659 (COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
2663 (v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 undef))),
2664 (COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
2668 (v2f16 (build_vector f16:$src0, (f16 undef))),
2669 (COPY $src0)
2695 (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
2696 (S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
2700 (v2i16 (DivergentBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
2701 …_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
2707 …(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 (trunc (srl_oneuse SReg_32:$src1, (…
2708 (v2i16 (S_PACK_LH_B32_B16 SReg_32:$src0, SReg_32:$src1))
2712 …(v2i16 (DivergentBinFrag<build_vector> (i16 SReg_32:$src0), (i16 (trunc (srl_oneuse SReg_32:$src1,…
2713 (v2i16 (V_BFI_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), SReg_32:$src0, SReg_32:$src1))
2718 (v2i16 (UniformBinFrag<build_vector> (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))),
2720 (S_PACK_HH_B32_B16 SReg_32:$src0, SReg_32:$src1)
2724 (v2i16 (DivergentBinFrag<build_vector> (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))),
2726 …:$src1, (i32 (V_MOV_B32_e32 (i32 0xffff0000))), (i32 (V_LSHRREV_B32_e64 (i32 16), SReg_32:$src0))))
2730 (v2f16 (UniformBinFrag<build_vector> (f16 SReg_32:$src0), (f16 SReg_32:$src1))),
2731 (S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
2735 (v2f16 (DivergentBinFrag<build_vector> (f16 SReg_32:$src0), (f16 SReg_32:$src1))),
2736 … SReg_32:$src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), SReg_32:$src0))))
2741 (v2f16 (is_canonicalized<build_vector> (f16 (VOP3Mods (f16 VGPR_32:$src0), i32:$src0_mods)),
2743 (V_PACK_B32_F16_e64 $src0_mods, VGPR_32:$src0, $src1_mods, VGPR_32:$src1)
2751 (v2i16 (build_vector (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))), (i16 SReg_32:$src1))),
2752 (v2i16 (S_PACK_HL_B32_B16 SReg_32:$src0, SReg_32:$src1))
2757 (v2f16 (scalar_to_vector f16:$src0)),
2758 (COPY $src0)
2762 (v2i16 (scalar_to_vector i16:$src0)),
2763 (COPY $src0)
2767 (v4i16 (scalar_to_vector i16:$src0)),
2768 (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
2772 (v4f16 (scalar_to_vector f16:$src0)),
2773 (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
2837 (UniformBinFrag<add> i32:$src0, (i32 NegSubInlineConst32:$src1)),
2838 (S_SUB_I32 SReg_32:$src0, NegSubInlineConst32:$src1)
2842 (DivergentBinFrag<add> i32:$src0, (i32 NegSubInlineConst32:$src1)),
2843 (V_SUB_U32_e64 VS_32:$src0, NegSubInlineConst32:$src1)> {
2848 (DivergentBinFrag<add> i32:$src0, (i32 NegSubInlineConst32:$src1)),
2849 (V_SUB_CO_U32_e64 VS_32:$src0, NegSubInlineConst32:$src1)> {
2959 (min (max_oneuse i32:$src0, i32:$src1),
2960 (max_oneuse (min_oneuse i32:$src0, i32:$src1), i32:$src2)),
2961 (med3Inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
2967 (max (min_oneuse i32:$src0, i32:$src1),
2968 (min_oneuse (max_oneuse i32:$src0, i32:$src1), i32:$src2)),
2969 (med3Inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
2981 (fmaxnum_like (fminnum_like_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
2983 (fminnum_like_oneuse (fmaxnum_like_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
2986 (med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
2991 (fmaxnum_like (fminnum_like_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
2993 (fminnum_like_oneuse (fmaxnum_like_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
2996 (med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE)
3007 (max (min_oneuse i16:$src0, i16:$src1),
3008 (min_oneuse (max_oneuse i16:$src0, i16:$src1), i16:$src2)),
3009 …(med3Inst SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1, SRCMODS.NONE, VSrc_b16:$src2…
3015 (min (max_oneuse i16:$src0, i16:$src1),
3016 (max_oneuse (min_oneuse i16:$src0, i16:$src1), i16:$src2)),
3017 …(med3Inst SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1, SRCMODS.NONE, VSrc_b16:$src2…
3026 (DivergentBinFrag<min_or_max> (max_or_min_oneuse i32:$src0, i32:$src1),
3028 (minmaxInst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
3034 (min_or_max (max_or_min_oneuse (VOP3Mods vt:$src0, i32:$src0_mods),
3037 (minmaxInst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
3148 let InOperandList = (ins type0:$src0, type0:$src1);
3154 let InOperandList = (ins type0:$src0, type0:$src1);
3161 let InOperandList = (ins type0:$src0);
3168 let InOperandList = (ins type0:$src0, type0:$src1);
3174 let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
3180 let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
3186 let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
3324 let InOperandList = (ins type0:$src0, unknown:$callee);
3335 let InOperandList = (ins type1:$src0);
3341 let InOperandList = (ins type1:$src0);