67 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)  in SIInstrInfo()  function in SIInstrInfo
111 bool SIInstrInfo::isReallyTriviallyReMaterializable(  in isReallyTriviallyReMaterializable()
169 bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {  in isIgnorableUse()
175 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
297 bool SIInstrInfo::getMemOperandsWithOffsetWidth(  in getMemOperandsWithOffsetWidth()
484 bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,  in shouldClusterMemOps()
527 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,  in shouldScheduleLoadsNear()
539 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,  in reportIllegalCopy()
556 static void indirectCopyToAGPR(const SIInstrInfo &TII,  in indirectCopyToAGPR()
666 static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,  in expandSGPRCopy()
714 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
1045 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {  in commuteOpcode()
1063 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,  in materializeImmediate()
1120 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {  in getPreferredSelectRegClass()
1124 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,  in insertVectorSelect()
1149     case SIInstrInfo::SCC_TRUE: {  in insertVectorSelect()
1163     case SIInstrInfo::SCC_FALSE: {  in insertVectorSelect()
1177     case SIInstrInfo::VCCNZ: {  in insertVectorSelect()
1191     case SIInstrInfo::VCCZ: {  in insertVectorSelect()
1205     case SIInstrInfo::EXECNZ: {  in insertVectorSelect()
1223     case SIInstrInfo::EXECZ: {  in insertVectorSelect()
1250 Register SIInstrInfo::insertEQ(MachineBasicBlock *MBB,  in insertEQ()
1263 Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,  in insertNE()
1276 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
1291 SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,  in getIndirectGPRIDXPseudo()
1392 SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,  in getIndirectRegWriteMovRelPseudo()
1517 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
1684 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1737 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
1742 void SIInstrInfo::insertNoops(MachineBasicBlock &MBB,  in insertNoops()
1753 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {  in insertReturn()
1771 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {  in getNumWaitStates()
1785 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
2170 SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {  in expandMovDPP64()
2233 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,  in swapSourceModifiers()
2283 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,  in commuteInstructionImpl()
2335 bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,  in findCommutedOpIndices()
2341 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,  in findCommutedOpIndices()
2358 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,  in isBranchOffsetInRange()
2374 MachineBasicBlock *SIInstrInfo::getBranchDestBlock(  in getBranchDestBlock()
2385 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,  in insertIndirectBranch()
2498 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {  in getBranchOpcode()
2500   case SIInstrInfo::SCC_TRUE:  in getBranchOpcode()
2502   case SIInstrInfo::SCC_FALSE:  in getBranchOpcode()
2504   case SIInstrInfo::VCCNZ:  in getBranchOpcode()
2506   case SIInstrInfo::VCCZ:  in getBranchOpcode()
2508   case SIInstrInfo::EXECNZ:  in getBranchOpcode()
2510   case SIInstrInfo::EXECZ:  in getBranchOpcode()
2517 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {  in getBranchPredicate()
2536 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,  in analyzeBranchImpl()
2579 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,  in analyzeBranch()
2622 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
2648 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
2708 bool SIInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
2722 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,  in canInsertSelect()
2764 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,  in insertSelect()
2871 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {  in isFoldableCopy()
2895 void SIInstrInfo::removeModOperands(MachineInstr &MI) const {  in removeModOperands()
2901 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
3137 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,  in checkInstOffsetsDoNotOverlap()
3161 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,  in areMemAccessesTriviallyDisjoint()
3216   if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {  in getFoldableImm()
3246 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,  in convertToThreeAddress()
3265   if (SIInstrInfo::isWMMA(MI)) {  in convertToThreeAddress()
3465 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
3495 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {  in isAlwaysGDS()
3505 bool SIInstrInfo::modifiesModeRegister(const MachineInstr &MI) {  in modifiesModeRegister()
3519 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {  in hasUnwantedEffectsWhenEXECEmpty()
3560 bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,  in mayReadEXEC()
3585 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
3605 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
3689 bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,  in isLiteralConstantLike()
3722 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,  in isImmOperandLegal()
3752 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
3764 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
3772 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
3778 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {  in hasAnyModifiersSet()
3783 bool SIInstrInfo::canShrink(const MachineInstr &MI,  in canShrink()
3852 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,  in buildShrunkInst()
3898 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
3954   if (SIInstrInfo::isVALU(MI)) {  in shouldReadExec()
3965       SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||  in shouldReadExec()
3966       SIInstrInfo::isSALU(MI) ||  in shouldReadExec()
3967       SIInstrInfo::isSMRD(MI))  in shouldReadExec()
3983 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
3986   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))  in verifyInstruction()
4685 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {  in getVALUOp()
4802 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,  in getRegClass()
4833 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
4850 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {  in legalizeOpWithMove()
4877 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,  in buildExtractSubReg()
4909 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
4931 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {  in swapOperands()
4938 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
4965 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
4976 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,  in isOperandLegal()
5070 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
5182 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,  in legalizeOperandsVOP3()
5268 Register SIInstrInfo::readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,  in readlaneVGPRToSGPR()
5310 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,  in legalizeOperandsSMRD()
5329 bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {  in moveFlatAddrToVGPR()
5410 void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,  in legalizeOperandsFLAT()
5428 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,  in legalizeGenericOperand()
5474 emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,  in emitLoadSRsrcFromVGPRLoop()
5584 loadSRsrcFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,  in loadSRsrcFromVGPR()
5670 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {  in extractRsrcPtr()
5712 SIInstrInfo::legalizeOperands(MachineInstr &MI,  in legalizeOperands()
6038 MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,  in moveToVALU()
6445 SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,  in moveScalarAddSub()
6480 void SIInstrInfo::lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,  in lowerSelect()
6556 void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,  in lowerScalarAbs()
6583 void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,  in lowerScalarXnor()
6648 void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,  in splitScalarNotBinop()
6677 void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,  in splitScalarBinOpN2()
6706 void SIInstrInfo::splitScalar64BitUnaryOp(  in splitScalar64BitUnaryOp()
6763 void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,  in splitScalar64BitAddSub()
6835 void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,  in splitScalar64BitBinaryOp()
6899 void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,  in splitScalar64BitXnor()
6941 void SIInstrInfo::splitScalar64BitBCNT(  in splitScalar64BitBCNT()
6978 void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,  in splitScalar64BitBFE()
7039 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
7076 void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,  in movePackToVALU()
7149 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,  in addSCCDefUsersToVALUWorklist()
7193 void SIInstrInfo::addSCCDefsToVALUWorklist(MachineOperand &Op,  in addSCCDefsToVALUWorklist()
7214 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
7264 Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,  in findUsedSGPR()
7333 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
7342 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
7367 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()
7391 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {  in isLowLatencyInstruction()
7397 bool SIInstrInfo::isHighLatencyDef(int Opc) const {  in isHighLatencyDef()
7402 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,  in isStackAccess()
7415 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,  in isSGPRStackAccess()
7423 unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
7437 unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
7451 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {  in getInstBundleSize()
7463 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
7524 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {  in mayAccessFlatAddressSpace()
7538 bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {  in isNonUniformBranchInstr()
7542 void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,  in convertNonUniformIfRegion()
7567 void SIInstrInfo::convertNonUniformLoopRegion(  in convertNonUniformLoopRegion()
7612 SIInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()
7625 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,  in CreateTargetPostRAHazardRecognizer()
7633 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {  in CreateTargetPostRAHazardRecognizer()
7640 SIInstrInfo::CreateTargetMIHazardRecognizer(const InstrItineraryData *II,  in CreateTargetMIHazardRecognizer()
7652 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
7657 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
7672 SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const {  in getSerializableMachineMemOperandTargetFlags()
7681 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {  in isBasicBlockPrologue()
7687 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
7702 MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
7723 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {  in isKillTerminator()
7733 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {  in getKillTerminatorFromPseudo()
7744 void SIInstrInfo::fixImplicitOperands(MachineInstr &MI) const {  in fixImplicitOperands()
7754 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {  in isBufferSMRD()
7797 bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,  in isLegalFLATOffset()
7824 SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,  in splitFlatOffset()
7891 bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {  in isAsmOnlyOpcode()
7911 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()
8142 MachineInstr *SIInstrInfo::createPHIDestinationCopy(  in createPHIDestinationCopy()
8157 MachineInstr *SIInstrInfo::createPHISourceCopy(  in createPHISourceCopy()
8177 bool llvm::SIInstrInfo::isWave32() const { return ST.isWave32(); }  in isWave32()
8179 MachineInstr *SIInstrInfo::foldMemoryOperandImpl(  in foldMemoryOperandImpl()
8216 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
8233 unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {  in getDSShaderTypeValue()
8255 bool SIInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,  in analyzeCompare()
8314 bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,  in optimizeCompareInstr()
8461 void SIInstrInfo::enforceOperandRCAlignment(MachineInstr &MI,  in enforceOperandRCAlignment()