Lines Matching refs:RI
69 RI(ST), ST(ST) { in SIInstrInfo()
575 const SIRegisterInfo &RI = TII.getRegisterInfo(); in indirectCopyToAGPR() local
580 if (!Def->definesRegister(SrcReg, &RI)) in indirectCopyToAGPR()
593 if (I->modifiesRegister(DefOp.getReg(), &RI)) in indirectCopyToAGPR()
621 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in indirectCopyToAGPR()
637 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
670 const SIRegisterInfo &RI = TII.getRegisterInfo(); in expandSGPRCopy() local
671 ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4); in expandSGPRCopy()
677 Register Reg = RI.getSubReg(DestReg, SubIdx); in expandSGPRCopy()
681 Register Src = RI.getSubReg(SrcReg, SubIdx); in expandSGPRCopy()
686 unsigned Channel = RI.getChannelFromSubReg(SubIdx); in expandSGPRCopy()
687 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy()
692 LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), RI.getSubReg(DestReg, SubIdx)) in expandSGPRCopy()
693 .addReg(RI.getSubReg(SrcReg, SubIdx)) in expandSGPRCopy()
711 LastMI->addRegisterKilled(SrcReg, &RI); in expandSGPRCopy()
718 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg); in copyPhysReg()
723 ((RI.getRegSizeInBits(*RC) == 16) ^ in copyPhysReg()
724 (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) { in copyPhysReg()
725 MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg; in copyPhysReg()
726 MCRegister Super = RI.get32BitRegister(RegToFix); in copyPhysReg()
727 assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix); in copyPhysReg()
736 RC = RI.getPhysRegClass(DestReg); in copyPhysReg()
859 const unsigned Size = RI.getRegSizeInBits(*RC); in copyPhysReg()
876 MCRegister NewDestReg = RI.get32BitRegister(DestReg); in copyPhysReg()
877 MCRegister NewSrcReg = RI.get32BitRegister(SrcReg); in copyPhysReg()
926 const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg); in copyPhysReg()
927 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) { in copyPhysReg()
949 const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg); in copyPhysReg()
950 if (RI.isSGPRClass(RC)) { in copyPhysReg()
951 if (!RI.isSGPRClass(SrcRC)) { in copyPhysReg()
955 const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg); in copyPhysReg()
963 if (RI.isAGPRClass(RC)) { in copyPhysReg()
964 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC)) in copyPhysReg()
966 else if (RI.hasVGPRs(SrcRC) || in copyPhysReg()
967 (ST.hasGFX90AInsts() && RI.isSGPRClass(SrcRC))) in copyPhysReg()
971 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) { in copyPhysReg()
973 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && in copyPhysReg()
974 (RI.isProperlyAlignedRC(*RC) && in copyPhysReg()
975 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) { in copyPhysReg()
995 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize); in copyPhysReg()
999 const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg); in copyPhysReg()
1013 indirectCopyToAGPR(*this, MBB, MI, DL, RI.getSubReg(DestReg, SubIdx), in copyPhysReg()
1014 RI.getSubReg(SrcReg, SubIdx), UseKill, *RS, in copyPhysReg()
1017 Register DstSubReg = RI.getSubReg(DestReg, SubIdx); in copyPhysReg()
1018 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx); in copyPhysReg()
1035 BuildMI(MBB, MI, DL, get(Opcode), RI.getSubReg(DestReg, SubIdx)) in copyPhysReg()
1036 .addReg(RI.getSubReg(SrcReg, SubIdx)); in copyPhysReg()
1099 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
1100 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
1109 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize); in materializeImmediate()
1114 get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx])); in materializeImmediate()
1132 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in insertVectorSelect()
1207 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1225 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1255 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertEQ()
1268 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertNE()
1278 if (RI.isAGPRClass(DstRC)) in getMovOpcode()
1280 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
1281 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
1282 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
1284 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
1536 if (RI.isSGPRClass(RC)) { in storeRegToStackSlot()
1558 if (RI.spillSGPRToVGPR()) in storeRegToStackSlot()
1563 unsigned Opcode = RI.isVectorSuperClass(RC) ? getAVSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1564 : RI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1702 if (RI.isSGPRClass(RC)) { in loadRegFromStackSlot()
1716 if (RI.spillSGPRToVGPR()) in loadRegFromStackSlot()
1726 unsigned Opcode = RI.isVectorSuperClass(RC) in loadRegFromStackSlot()
1728 : RI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
1851 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
1852 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
1888 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) { in expandPostRAPseudo()
1901 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
1904 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
1925 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
1926 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
1997 if (RI.hasVGPRs(EltRC)) { in expandPostRAPseudo()
2000 Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64 in expandPostRAPseudo()
2012 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2046 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2085 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2098 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo()
2099 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo()
2191 MovDPP.addDef(RI.getSubReg(Dst, Sub)); in expandMovDPP64()
2209 MovDPP.addReg(RI.getSubReg(Src, Sub)); in expandMovDPP64()
2739 return RI.hasVGPRs(RC) && NumInsts <= 6; in canInsertSelect()
2757 return RI.isSGPRClass(RC); in canInsertSelect()
2776 unsigned DstSize = RI.getRegSizeInBits(*DstRC); in insertSelect()
2930 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg); in FoldImmediate()
2937 if (RI.isAGPR(*MRI, DstReg)) { in FoldImmediate()
2952 DstReg = RI.get32BitRegister(DstReg); in FoldImmediate()
2992 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
2995 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
3053 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) || in FoldImmediate()
3056 RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))) in FoldImmediate()
3070 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) || in FoldImmediate()
3072 RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
3144 Dummy0, &RI) || in checkInstOffsetsDoNotOverlap()
3146 Dummy1, &RI)) in checkInstOffsetsDoNotOverlap()
3343 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) { in convertToThreeAddress()
3489 return MI.modifiesRegister(AMDGPU::EXEC, &RI) || in isSchedulingBoundary()
3567 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg())) in mayReadEXEC()
3571 return MI.readsRegister(AMDGPU::EXEC, &RI); in mayReadEXEC()
3582 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI); in mayReadEXEC()
3740 return RI.opCanUseInlineConstant(OpInfo.OperandType); in isImmOperandLegal()
3743 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType)) in isImmOperandLegal()
3796 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
3808 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
3819 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
3914 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
4016 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
4104 const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg); in verifyInstruction()
4105 if (RI.hasVectorRegisters(RC) && MO.getSubReg()) { in verifyInstruction()
4107 RI.getSubRegClass(RC, MO.getSubReg()); in verifyInstruction()
4108 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
4114 if (!RC || !RI.isProperlyAlignedRC(*RC)) { in verifyInstruction()
4124 const TargetRegisterClass *RC = RI.getRegClass(RegClass); in verifyInstruction()
4148 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
4247 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32; in verifyInstruction()
4307 return !RI.regsOverlap(SGPRUsed, SGPR); in verifyInstruction()
4452 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) { in verifyInstruction()
4609 (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) { in verifyInstruction()
4615 (RI.isAGPR(MRI, Data->getReg()) != RI.isAGPR(MRI, Data2->getReg()))) { in verifyInstruction()
4621 if ((Dst && RI.isAGPR(MRI, Dst->getReg())) || in verifyInstruction()
4622 (Data && RI.isAGPR(MRI, Data->getReg())) || in verifyInstruction()
4623 (Data2 && RI.isAGPR(MRI, Data2->getReg()))) { in verifyInstruction()
4638 return !(RI.getHWRegIndex(Reg) & 1); in verifyInstruction()
4640 return RI.getRegSizeInBits(RC) > 32 && RI.isProperlyAlignedRC(RC) && in verifyInstruction()
4641 !(RI.getChannelFromSubReg(Op->getSubReg()) & 1); in verifyInstruction()
4667 if (Src->isReg() && RI.isSGPRReg(MRI, Src->getReg())) { in verifyInstruction()
4699 RI.isAGPR(MRI, MI.getOperand(0).getReg()) ? in getVALUOp()
4767 adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI, in adjustAllocatableRegClass() argument
4799 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
4829 return adjustAllocatableRegClass(ST, RI, MF.getRegInfo(), TID, RegClass, in getRegClass()
4843 return RI.getPhysRegClass(Reg); in getOpRegClass()
4847 return adjustAllocatableRegClass(ST, RI, MRI, Desc, RCID, true); in getOpRegClass()
4856 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
4857 unsigned Size = RI.getRegSizeInBits(*RC); in legalizeOpWithMove()
4861 else if (RI.isSGPRClass(RC)) in legalizeOpWithMove()
4864 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove()
4865 const TargetRegisterClass *VRC64 = RI.getVGPR64Class(); in legalizeOpWithMove()
4866 if (RI.getCommonSubClass(VRC64, VRC)) in legalizeOpWithMove()
4946 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand()
4954 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand()
4958 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
4983 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; in isOperandLegal()
5025 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal()
5039 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()
5043 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()
5049 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
5054 RI.isSGPRReg(MRI, MO->getReg())) in isOperandLegal()
5085 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) || in legalizeOperandsVOP2()
5094 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
5100 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
5111 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg())) in legalizeOperandsVOP2()
5114 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg())) in legalizeOperandsVOP2()
5126 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
5198 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { in legalizeOperandsVOP3()
5204 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) { in legalizeOperandsVOP3()
5243 if (RI.hasAGPRs(RI.getRegClassForReg(MRI, MO.getReg())) && in legalizeOperandsVOP3()
5249 if (!RI.isSGPRClass(RI.getRegClassForReg(MRI, MO.getReg()))) in legalizeOperandsVOP3()
5271 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
5273 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
5275 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
5276 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
5296 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5305 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5318 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { in legalizeOperandsSMRD()
5323 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) { in legalizeOperandsSMRD()
5345 if (RI.isSGPRReg(MRI, SAddr.getReg())) in moveFlatAddrToVGPR()
5418 if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg()))) in legalizeOperandsFLAT()
5437 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
5438 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
5465 if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) && in legalizeGenericOperand()
5752 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
5762 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
5768 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
5769 ? RI.getEquivalentAGPRClass(SRC) in legalizeOperands()
5770 : RI.getEquivalentVGPRClass(SRC); in legalizeOperands()
5772 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
5773 ? RI.getEquivalentAGPRClass(VRC) in legalizeOperands()
5774 : RI.getEquivalentVGPRClass(VRC); in legalizeOperands()
5803 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()
5813 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
5843 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg()))) in legalizeOperands()
5856 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) in legalizeOperands()
5860 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) in legalizeOperands()
5869 if (!RI.isSGPRClass(MRI.getRegClass(Dest->getReg()))) { in legalizeOperands()
5900 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), in legalizeOperands()
5901 RI.getRegClass(RsrcRC))) { in legalizeOperands()
5930 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in legalizeOperands()
6185 Register VCC = RI.getVCC(); in moveToVALU()
6241 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in moveToVALU()
6252 Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass( in moveToVALU()
6281 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg())); in moveToVALU()
6320 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALU()
6407 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { in moveToVALU()
6507 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in lowerSelect()
6518 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != in lowerSelect()
6611 RI.isSGPRClass(MRI.getRegClass(Src0.getReg())); in lowerScalarXnor()
6613 RI.isSGPRClass(MRI.getRegClass(Src1.getReg())); in lowerScalarXnor()
6723 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6729 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
6730 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6770 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in splitScalar64BitAddSub()
6787 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6788 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6853 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6858 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6870 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
6871 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6919 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) { in splitScalar64BitXnor()
6960 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
7064 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
7164 int SCCIdx = MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI); in addSCCDefUsersToVALUWorklist()
7181 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) in addSCCDefUsersToVALUWorklist()
7205 if (MI.modifiesRegister(AMDGPU::VCC, &RI)) in addSCCDefsToVALUWorklist()
7207 if (MI.definesRegister(AMDGPU::SCC, &RI)) { in addSCCDefsToVALUWorklist()
7231 if (RI.isAGPRClass(SrcRC)) { in getDestEquivalentVGPRClass()
7232 if (RI.isAGPRClass(NewDstRC)) in getDestEquivalentVGPRClass()
7239 NewDstRC = RI.getEquivalentAGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
7242 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
7248 if (RI.isVGPRClass(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
7251 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
7295 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR()
7296 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
7303 if (RI.isSGPRClass(RegRC)) in findUsedSGPR()
7552 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformIfRegion()
7579 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
7580 Register BackEdgeReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
7587 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
7683 MI.modifiesRegister(AMDGPU::EXEC, &RI); in isBasicBlockPrologue()
7695 Register UnusedCarry = MRI.createVirtualRegister(RI.getBoolRC()); in getAddNoCarry()
7696 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
7712 ? Register(RI.getVCC()) in getAddNoCarry()
7713 : RS.scavengeRegister(RI.getBoolRC(), I, 0, false); in getAddNoCarry()
7764 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()
8397 if (I->modifiesRegister(AMDGPU::SCC, &RI) || in optimizeCompareInstr()
8398 I->killsRegister(AMDGPU::SCC, &RI)) in optimizeCompareInstr()
8478 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment()