1131   const TargetRegisterClass *BoolXExecRC =  in insertVectorSelect()  local
1137     Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1150       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1164       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1180       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1194       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1206       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1224       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
5488   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in emitLoadSRsrcFromVGPRLoop()  local
5526     Register NewCondReg = MRI.createVirtualRegister(BoolXExecRC);  in emitLoadSRsrcFromVGPRLoop()
5539       Register AndReg = MRI.createVirtualRegister(BoolXExecRC);  in emitLoadSRsrcFromVGPRLoop()
5562   Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);  in emitLoadSRsrcFromVGPRLoop()
5602   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in loadSRsrcFromVGPR()  local
5604   Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);  in loadSRsrcFromVGPR()
5930       const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in legalizeOperands()  local
5931       Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);  in legalizeOperands()
5932       Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);  in legalizeOperands()