Lines Matching refs:SL
1635 const SDLoc &SL, in lowerKernArgParameterPtr() argument
1653 return DAG.getConstant(0, SL, PtrVT); in lowerKernArgParameterPtr()
1656 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL, in lowerKernArgParameterPtr()
1659 return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Offset)); in lowerKernArgParameterPtr()
1663 const SDLoc &SL) const { in getImplicitArgPtr()
1666 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset); in getImplicitArgPtr()
1670 const SDLoc &SL) const { in getLDSKernelId()
1676 return DAG.getConstant(KnownSize.value(), SL, MVT::i32); in getLDSKernelId()
1681 const SDLoc &SL, SDValue Val, in convertArgType() argument
1690 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
1691 DAG.getConstant(0, SL, MVT::i32)); in convertArgType()
1698 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT)); in convertArgType()
1702 Val = getFPExtOrFPRound(DAG, Val, SL, VT); in convertArgType()
1704 Val = DAG.getSExtOrTrunc(Val, SL, VT); in convertArgType()
1706 Val = DAG.getZExtOrTrunc(Val, SL, VT); in convertArgType()
1712 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, in lowerKernargMemParameter() argument
1729 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset); in lowerKernargMemParameter()
1730 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4), in lowerKernargMemParameter()
1734 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32); in lowerKernargMemParameter()
1735 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt); in lowerKernargMemParameter()
1737 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
1738 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal); in lowerKernargMemParameter()
1739 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg); in lowerKernargMemParameter()
1742 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL); in lowerKernargMemParameter()
1745 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset); in lowerKernargMemParameter()
1746 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment, in lowerKernargMemParameter()
1750 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg); in lowerKernargMemParameter()
1751 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL); in lowerKernargMemParameter()
1755 const SDLoc &SL, SDValue Chain, in lowerStackParameter() argument
1797 ExtType, SL, VA.getLocVT(), Chain, FIN, in lowerStackParameter()
2877 SDLoc SL; in passSpecialInputs() local
2896 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y, in passSpecialInputs()
2897 DAG.getShiftAmountConstant(10, MVT::i32, SL)); in passSpecialInputs()
2899 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y; in passSpecialInputs()
2905 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z, in passSpecialInputs()
2906 DAG.getShiftAmountConstant(20, MVT::i32, SL)); in passSpecialInputs()
2908 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z; in passSpecialInputs()
4579 SDLoc SL(Op); in splitUnaryVectorOp() local
4580 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo, in splitUnaryVectorOp()
4582 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi, in splitUnaryVectorOp()
4604 SDLoc SL(Op); in splitBinaryVectorOp() local
4606 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, in splitBinaryVectorOp()
4608 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp()
4633 SDLoc SL(Op); in splitTernaryVectorOp() local
4636 SDValue OpLo = DAG.getNode(Opc, SL, ResVT.first, Lo0, Lo1, Lo2, in splitTernaryVectorOp()
4638 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
4916 SDLoc SL(N); in lowerFCMPIntrinsic() local
4919 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in lowerFCMPIntrinsic()
4920 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in lowerFCMPIntrinsic()
4927 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic()
4931 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
4938 SDLoc SL(N); in lowerBALLOTIntrinsic() local
4942 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0), in lowerBALLOTIntrinsic()
4948 return DAG.getConstant(0, SL, VT); in lowerBALLOTIntrinsic()
4960 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, Exec, VT); in lowerBALLOTIntrinsic()
4967 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32), in lowerBALLOTIntrinsic()
4968 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
4991 SDLoc SL(N); in ReplaceNodeResults() local
4992 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32, in ReplaceNodeResults()
4994 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt)); in ReplaceNodeResults()
5003 SDLoc SL(N); in ReplaceNodeResults() local
5017 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1)); in ReplaceNodeResults()
5019 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1); in ReplaceNodeResults()
5020 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt)); in ReplaceNodeResults()
5044 SDLoc SL(N); in ReplaceNodeResults() local
5047 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
5048 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
5052 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS); in ReplaceNodeResults()
5053 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS); in ReplaceNodeResults()
5057 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT, in ReplaceNodeResults()
5061 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
5062 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect)); in ReplaceNodeResults()
5069 SDLoc SL(N); in ReplaceNodeResults() local
5070 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0)); in ReplaceNodeResults()
5072 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32, in ReplaceNodeResults()
5074 DAG.getConstant(0x80008000, SL, MVT::i32)); in ReplaceNodeResults()
5075 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op)); in ReplaceNodeResults()
5082 SDLoc SL(N); in ReplaceNodeResults() local
5083 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0)); in ReplaceNodeResults()
5085 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32, in ReplaceNodeResults()
5087 DAG.getConstant(0x7fff7fff, SL, MVT::i32)); in ReplaceNodeResults()
5088 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op)); in ReplaceNodeResults()
5327 SDLoc SL(Op); in lowerXMULO() local
5338 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), SL, MVT::i32); in lowerXMULO()
5339 SDValue Result = DAG.getNode(ISD::SHL, SL, VT, LHS, ShiftAmt); in lowerXMULO()
5340 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, in lowerXMULO()
5342 SL, VT, Result, ShiftAmt), in lowerXMULO()
5344 return DAG.getMergeValues({ Result, Overflow }, SL); in lowerXMULO()
5348 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS); in lowerXMULO()
5350 SL, VT, LHS, RHS); in lowerXMULO()
5353 ? DAG.getNode(ISD::SRA, SL, VT, Result, in lowerXMULO()
5354 DAG.getConstant(VT.getScalarSizeInBits() - 1, SL, MVT::i32)) in lowerXMULO()
5355 : DAG.getConstant(0, SL, VT); in lowerXMULO()
5356 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE); in lowerXMULO()
5358 return DAG.getMergeValues({ Result, Overflow }, SL); in lowerXMULO()
5398 SDLoc SL(Op); in lowerTrapEndpgm() local
5400 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain); in lowerTrapEndpgm()
5416 SDLoc SL(Op); in lowerTrapHsaQueuePtr() local
5423 loadImplicitKernelArgument(DAG, MVT::i64, SL, Align(8), QUEUE_PTR); in lowerTrapHsaQueuePtr()
5433 QueuePtr = DAG.getConstant(0, SL, MVT::i64); in lowerTrapHsaQueuePtr()
5441 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01, in lowerTrapHsaQueuePtr()
5447 DAG.getTargetConstant(TrapID, SL, MVT::i16), in lowerTrapHsaQueuePtr()
5451 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops); in lowerTrapHsaQueuePtr()
5456 SDLoc SL(Op); in lowerTrapHsa() local
5462 DAG.getTargetConstant(TrapID, SL, MVT::i16) in lowerTrapHsa()
5464 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops); in lowerTrapHsa()
5468 SDLoc SL(Op); in lowerDEBUGTRAP() local
5486 DAG.getTargetConstant(TrapID, SL, MVT::i16) in lowerDEBUGTRAP()
5488 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops); in lowerDEBUGTRAP()
5568 SDLoc SL(Op); in lowerADDRSPACECAST() local
5572 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64); in lowerADDRSPACECAST()
5584 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src); in lowerADDRSPACECAST()
5590 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32); in lowerADDRSPACECAST()
5591 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE); in lowerADDRSPACECAST()
5593 return DAG.getNode(ISD::SELECT, SL, MVT::i32, NonNull, Ptr, in lowerADDRSPACECAST()
5603 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG); in lowerADDRSPACECAST()
5605 DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture); in lowerADDRSPACECAST()
5606 CvtPtr = DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr); in lowerADDRSPACECAST()
5612 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32); in lowerADDRSPACECAST()
5615 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE); in lowerADDRSPACECAST()
5617 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull, CvtPtr, in lowerADDRSPACECAST()
5626 SDValue Hi = DAG.getConstant(Info->get32BitAddressHighBits(), SL, MVT::i32); in lowerADDRSPACECAST()
5627 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Hi); in lowerADDRSPACECAST()
5628 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in lowerADDRSPACECAST()
5633 return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src); in lowerADDRSPACECAST()
5639 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc()); in lowerADDRSPACECAST()
5660 SDLoc SL(Op); in lowerINSERT_SUBVECTOR() local
5663 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins, in lowerINSERT_SUBVECTOR()
5664 DAG.getConstant(I, SL, MVT::i32)); in lowerINSERT_SUBVECTOR()
5665 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt, in lowerINSERT_SUBVECTOR()
5666 DAG.getConstant(IdxVal + I, SL, MVT::i32)); in lowerINSERT_SUBVECTOR()
5680 SDLoc SL(Op); in lowerINSERT_VECTOR_ELT() local
5686 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec); in lowerINSERT_VECTOR_ELT()
5688 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT()
5689 DAG.getConstant(0, SL, MVT::i32)); in lowerINSERT_VECTOR_ELT()
5690 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT()
5691 DAG.getConstant(1, SL, MVT::i32)); in lowerINSERT_VECTOR_ELT()
5693 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf); in lowerINSERT_VECTOR_ELT()
5694 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
5698 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16, in lowerINSERT_VECTOR_ELT()
5700 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal), in lowerINSERT_VECTOR_ELT()
5701 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32)); in lowerINSERT_VECTOR_ELT()
5703 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf); in lowerINSERT_VECTOR_ELT()
5706 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) : in lowerINSERT_VECTOR_ELT()
5707 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf }); in lowerINSERT_VECTOR_ELT()
5709 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat); in lowerINSERT_VECTOR_ELT()
5726 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32); in lowerINSERT_VECTOR_ELT()
5727 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor); in lowerINSERT_VECTOR_ELT()
5728 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5729 DAG.getConstant(0xffff, SL, IntVT), in lowerINSERT_VECTOR_ELT()
5733 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5734 DAG.getSplatBuildVector(VecVT, SL, InsVal)); in lowerINSERT_VECTOR_ELT()
5737 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
5740 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT()
5741 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5742 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
5745 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS); in lowerINSERT_VECTOR_ELT()
5747 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI); in lowerINSERT_VECTOR_ELT()
5752 SDLoc SL(Op); in lowerEXTRACT_VECTOR_ELT() local
5778 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i64, V2, in lowerEXTRACT_VECTOR_ELT()
5779 DAG.getConstant(0, SL, MVT::i32))); in lowerEXTRACT_VECTOR_ELT()
5781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i64, V2, in lowerEXTRACT_VECTOR_ELT()
5782 DAG.getConstant(1, SL, MVT::i32))); in lowerEXTRACT_VECTOR_ELT()
5789 Parts[P] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i64, V2, in lowerEXTRACT_VECTOR_ELT()
5790 DAG.getConstant(P, SL, MVT::i32)); in lowerEXTRACT_VECTOR_ELT()
5793 Lo = DAG.getBitcast(LoVT, DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i64, in lowerEXTRACT_VECTOR_ELT()
5795 Hi = DAG.getBitcast(HiVT, DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i64, in lowerEXTRACT_VECTOR_ELT()
5802 SDValue IdxMask = DAG.getConstant(NElem / 2 - 1, SL, IdxVT); in lowerEXTRACT_VECTOR_ELT()
5803 SDValue NewIdx = DAG.getNode(ISD::AND, SL, IdxVT, Idx, IdxMask); in lowerEXTRACT_VECTOR_ELT()
5804 SDValue Half = DAG.getSelectCC(SL, Idx, IdxMask, Hi, Lo, ISD::SETUGT); in lowerEXTRACT_VECTOR_ELT()
5805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Half, NewIdx); in lowerEXTRACT_VECTOR_ELT()
5817 Vec = DAG.getAnyExtOrTrunc(Src, SL, IntVT); in lowerEXTRACT_VECTOR_ELT()
5823 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32); in lowerEXTRACT_VECTOR_ELT()
5826 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor); in lowerEXTRACT_VECTOR_ELT()
5828 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerEXTRACT_VECTOR_ELT()
5829 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx); in lowerEXTRACT_VECTOR_ELT()
5832 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt); in lowerEXTRACT_VECTOR_ELT()
5833 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result); in lowerEXTRACT_VECTOR_ELT()
5836 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT); in lowerEXTRACT_VECTOR_ELT()
5846 SDLoc SL(Op); in lowerVECTOR_SHUFFLE() local
5870 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
5872 DAG.getConstant(EltIdx, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
5883 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE()
5884 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
5887 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE()
5888 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
5889 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 })); in lowerVECTOR_SHUFFLE()
5893 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
5902 SDLoc SL(Op); in lowerSCALAR_TO_VECTOR() local
5909 return DAG.getBuildVector(ResultVT, SL, VElts); in lowerSCALAR_TO_VECTOR()
5914 SDLoc SL(Op); in lowerBUILD_VECTOR() local
5930 SDValue Lo = DAG.getBuildVector(HalfVT, SL, LoOps); in lowerBUILD_VECTOR()
5931 SDValue Hi = DAG.getBuildVector(HalfVT, SL, HiOps); in lowerBUILD_VECTOR()
5933 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, HalfIntVT, Lo); in lowerBUILD_VECTOR()
5934 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, HalfIntVT, Hi); in lowerBUILD_VECTOR()
5936 SDValue Blend = DAG.getBuildVector(MVT::getVectorVT(HalfIntVT, 2), SL, in lowerBUILD_VECTOR()
5938 return DAG.getNode(ISD::BITCAST, SL, VT, Blend); in lowerBUILD_VECTOR()
5953 SDValue Vec = DAG.getBuildVector(QuarterVT, SL, Parts[P]); in lowerBUILD_VECTOR()
5954 Casts[P] = DAG.getNode(ISD::BITCAST, SL, QuarterIntVT, Vec); in lowerBUILD_VECTOR()
5958 DAG.getBuildVector(MVT::getVectorVT(QuarterIntVT, 4), SL, Casts); in lowerBUILD_VECTOR()
5959 return DAG.getNode(ISD::BITCAST, SL, VT, Blend); in lowerBUILD_VECTOR()
5970 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo); in lowerBUILD_VECTOR()
5971 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
5972 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo); in lowerBUILD_VECTOR()
5975 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi); in lowerBUILD_VECTOR()
5976 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi); in lowerBUILD_VECTOR()
5978 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi, in lowerBUILD_VECTOR()
5979 DAG.getConstant(16, SL, MVT::i32)); in lowerBUILD_VECTOR()
5981 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi); in lowerBUILD_VECTOR()
5983 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo); in lowerBUILD_VECTOR()
5984 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
5986 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi); in lowerBUILD_VECTOR()
5987 return DAG.getNode(ISD::BITCAST, SL, VT, Or); in lowerBUILD_VECTOR()
6126 SDLoc SL(Op); in lowerImplicitZextParam() local
6128 DAG, MVT::i32, MVT::i32, SL, DAG.getEntryNode(), Offset, Align(4), false); in lowerImplicitZextParam()
6130 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
6754 SDLoc SL(Op); in lowerWorkitemID() local
6758 return DAG.getConstant(0, SL, MVT::i32); in lowerWorkitemID()
6773 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Val, in lowerWorkitemID()
7080 SDLoc SL(Op); in LowerINTRINSIC_WO_CHAIN() local
7083 SDValue Aperture = getSegmentAperture(AS, SL, DAG); in LowerINTRINSIC_WO_CHAIN()
7087 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
7088 DAG.getConstant(1, SL, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7089 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
8522 const SDLoc &SL, EVT VT) { in getLoadExtOrTrunc() argument
8524 return DAG.getNode(ISD::TRUNCATE, SL, VT, Op); in getLoadExtOrTrunc()
8528 return DAG.getNode(ISD::SIGN_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
8530 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
8532 return DAG.getNode(ISD::ANY_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
8560 SDLoc SL(Ld); in widenLoad() local
8568 ISD::UNINDEXED, ISD::NON_EXTLOAD, MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
8582 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad, in widenLoad()
8586 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
8598 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT); in widenLoad()
8602 Cvt = DAG.getNode(ISD::BITCAST, SL, VT, Cvt); in widenLoad()
8604 return DAG.getMergeValues({ Cvt, NewLoad.getValue(1) }, SL); in widenLoad()
8801 SDLoc SL(Op); in lowerFastUnsafeFDIV() local
8828 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0)); in lowerFastUnsafeFDIV()
8831 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8837 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
8838 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS); in lowerFastUnsafeFDIV()
8844 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8845 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags); in lowerFastUnsafeFDIV()
8850 SDLoc SL(Op); in lowerFastUnsafeFDIV64() local
8861 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64()
8862 SDValue One = DAG.getConstantFP(1.0, SL, VT); in lowerFastUnsafeFDIV64()
8864 SDValue R = DAG.getNode(AMDGPUISD::RCP, SL, VT, Y); in lowerFastUnsafeFDIV64()
8865 SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64()
8867 R = DAG.getNode(ISD::FMA, SL, VT, Tmp0, R, R); in lowerFastUnsafeFDIV64()
8868 SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64()
8869 R = DAG.getNode(ISD::FMA, SL, VT, Tmp1, R, R); in lowerFastUnsafeFDIV64()
8870 SDValue Ret = DAG.getNode(ISD::FMUL, SL, VT, X, R); in lowerFastUnsafeFDIV64()
8871 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X); in lowerFastUnsafeFDIV64()
8872 return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret); in lowerFastUnsafeFDIV64()
8875 static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, in getFPBinOp() argument
8879 return DAG.getNode(Opcode, SL, VT, A, B, Flags); in getFPBinOp()
8892 return DAG.getNode(Opcode, SL, VTList, in getFPBinOp()
8897 static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, in getFPTernOp() argument
8901 return DAG.getNode(Opcode, SL, VT, {A, B, C}, Flags); in getFPTernOp()
8914 return DAG.getNode(Opcode, SL, VTList, in getFPTernOp()
8923 SDLoc SL(Op); in LowerFDIV16() local
8927 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in LowerFDIV16()
8928 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in LowerFDIV16()
8930 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1); in LowerFDIV16()
8931 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1); in LowerFDIV16()
8933 SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32); in LowerFDIV16()
8934 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8936 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0); in LowerFDIV16()
8941 SDLoc SL(Op); in lowerFDIV_FAST() local
8945 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in lowerFDIV_FAST()
8948 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32); in lowerFDIV_FAST()
8951 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32); in lowerFDIV_FAST()
8953 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); in lowerFDIV_FAST()
8958 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT); in lowerFDIV_FAST()
8960 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One); in lowerFDIV_FAST()
8963 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3); in lowerFDIV_FAST()
8966 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1); in lowerFDIV_FAST()
8968 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); in lowerFDIV_FAST()
8970 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); in lowerFDIV_FAST()
8976 const SDLoc &SL, const GCNSubtarget *ST) { in getSPDenormModeValue() argument
8983 return DAG.getTargetConstant(Mode, SL, MVT::i32); in getSPDenormModeValue()
8997 SDLoc SL(Op); in LowerFDIV32() local
9001 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); in LowerFDIV32()
9005 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, in LowerFDIV32()
9007 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, in LowerFDIV32()
9011 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, in LowerFDIV32()
9013 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
9019 const SDValue BitField = DAG.getTargetConstant(Denorm32Reg, SL, MVT::i32); in LowerFDIV32()
9033 getSPDenormModeValue(FP_DENORM_FLUSH_NONE, DAG, SL, Subtarget); in LowerFDIV32()
9035 EnableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, BindParamVTs, in LowerFDIV32()
9039 SL, MVT::i32); in LowerFDIV32()
9041 DAG.getMachineNode(AMDGPU::S_SETREG_B32, SL, BindParamVTs, in LowerFDIV32()
9051 NegDivScale0 = DAG.getMergeValues(Ops, SL); in LowerFDIV32()
9054 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
9057 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32()
9060 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled, in LowerFDIV32()
9063 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, in LowerFDIV32()
9066 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, in LowerFDIV32()
9069 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, in LowerFDIV32()
9076 getSPDenormModeValue(FP_DENORM_FLUSH_IN_FLUSH_OUT, DAG, SL, Subtarget); in LowerFDIV32()
9078 DisableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, MVT::Other, in LowerFDIV32()
9083 DAG.getConstant(FP_DENORM_FLUSH_IN_FLUSH_OUT, SL, MVT::i32); in LowerFDIV32()
9086 AMDGPU::S_SETREG_B32, SL, MVT::Other, in LowerFDIV32()
9090 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in LowerFDIV32()
9096 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, in LowerFDIV32()
9099 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS, Flags); in LowerFDIV32()
9106 SDLoc SL(Op); in LowerFDIV64() local
9110 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFDIV64()
9114 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X); in LowerFDIV64()
9116 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
9118 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64()
9120 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
9122 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
9124 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
9126 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64()
9128 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
9129 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
9131 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64, in LowerFDIV64()
9140 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32); in LowerFDIV64()
9143 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); in LowerFDIV64()
9144 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y); in LowerFDIV64()
9145 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0); in LowerFDIV64()
9146 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64()
9148 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi); in LowerFDIV64()
9149 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi); in LowerFDIV64()
9152 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi); in LowerFDIV64()
9154 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi); in LowerFDIV64()
9156 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ); in LowerFDIV64()
9157 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ); in LowerFDIV64()
9158 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen); in LowerFDIV64()
9163 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64, in LowerFDIV64()
9166 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X); in LowerFDIV64()
9403 SDLoc SL(N); in performSHLPtrCombine() local
9406 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); in performSHLPtrCombine()
9407 SDValue COffset = DAG.getConstant(Offset, SL, VT); in performSHLPtrCombine()
9414 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset, Flags); in performSHLPtrCombine()
9434 SDLoc SL(N); in performMemSDNodeCombine() local
9467 const SDLoc &SL, in splitBinaryBitConstantOp() argument
9481 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi); in splitBinaryBitConstantOp()
9603 SDLoc SL(N); in performAndCombine() local
9604 SDValue BFE = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in performAndCombine()
9606 DAG.getConstant(Offset, SL, MVT::i32), in performAndCombine()
9607 DAG.getConstant(Bits, SL, MVT::i32)); in performAndCombine()
9609 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
9859 SDLoc SL(N); in performOrCombine() local
9862 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc); in performOrCombine()
9867 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in performOrCombine()
9869 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performOrCombine()
10202 SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const { in getCanonicalConstantFP() argument
10205 return DAG.getConstantFP(0.0, SL, VT); in getCanonicalConstantFP()
10212 return DAG.getConstantFP(CanonicalQNaN, SL, VT); in getCanonicalConstantFP()
10220 return DAG.getConstantFP(CanonicalQNaN, SL, VT); in getCanonicalConstantFP()
10224 return DAG.getConstantFP(C, SL, VT); in getCanonicalConstantFP()
10258 SDLoc SL(N); in performFCanonicalizeCombine() local
10268 NewElts[I] = getCanonicalConstantFP(DAG, SL, EltVT, in performFCanonicalizeCombine()
10274 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op); in performFCanonicalizeCombine()
10284 NewElts[1]: DAG.getConstantFP(0.0f, SL, EltVT); in performFCanonicalizeCombine()
10289 NewElts[0] : DAG.getConstantFP(0.0f, SL, EltVT); in performFCanonicalizeCombine()
10292 return DAG.getBuildVector(VT, SL, NewElts); in performFCanonicalizeCombine()
10306 SDLoc SL(N); in performFCanonicalizeCombine() local
10307 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT, in performFCanonicalizeCombine()
10309 SDValue Canon1 = getCanonicalConstantFP(DAG, SL, VT, CRHS->getValueAPF()); in performFCanonicalizeCombine()
10312 return DAG.getNode(N0.getOpcode(), SL, VT, Canon0, Canon1); in performFCanonicalizeCombine()
10341 SelectionDAG &DAG, const SDLoc &SL, in performIntMed3ImmCombine() argument
10362 return DAG.getNode(Med3Opc, SL, VT, in performIntMed3ImmCombine()
10371 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
10372 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
10373 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
10375 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3); in performIntMed3ImmCombine()
10376 return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3); in performIntMed3ImmCombine()
10395 const SDLoc &SL, in performFPMed3ImmCombine() argument
10420 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Op0.getOperand(0)); in performFPMed3ImmCombine()
10439 return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), in performFPMed3ImmCombine()
10536 SDLoc SL(N); in performFMed3Combine() local
10546 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src2); in performFMed3Combine()
10567 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0); in performFMed3Combine()
10645 SDLoc SL(N); in performExtractVectorEltCombine() local
10648 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine()
10650 return DAG.getNode(Vec.getOpcode(), SL, EltVT, Elt); in performExtractVectorEltCombine()
10659 SDLoc SL(N); in performExtractVectorEltCombine() local
10680 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine()
10682 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine()
10687 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags()); in performExtractVectorEltCombine()
10697 SDLoc SL(N); in performExtractVectorEltCombine() local
10701 SDValue IC = DAG.getVectorIdxConstant(I, SL); in performExtractVectorEltCombine()
10702 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC); in performExtractVectorEltCombine()
10706 V = DAG.getSelectCC(SL, Idx, IC, Elt, V, ISD::SETEQ); in performExtractVectorEltCombine()
10729 SDLoc SL(N); in performExtractVectorEltCombine() local
10731 SDValue Cast = DAG.getNode(ISD::BITCAST, SL, NewVT, Vec); in performExtractVectorEltCombine()
10734 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Cast, in performExtractVectorEltCombine()
10735 DAG.getConstant(EltIdx, SL, MVT::i32)); in performExtractVectorEltCombine()
10737 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine()
10738 DAG.getConstant(LeftoverBitIdx, SL, MVT::i32)); in performExtractVectorEltCombine()
10741 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl); in performExtractVectorEltCombine()
10743 return DAG.getNode(ISD::BITCAST, SL, EltVT, Trunc); in performExtractVectorEltCombine()
10763 SDLoc SL(N); in performInsertVectorEltCombine() local
10769 SDValue IC = DAG.getConstant(I, SL, IdxVT); in performInsertVectorEltCombine()
10770 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC); in performInsertVectorEltCombine()
10771 SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ); in performInsertVectorEltCombine()
10775 return DAG.getBuildVector(VecVT, SL, Ops); in performInsertVectorEltCombine()
10834 SDLoc SL(N); in reassociateScalarOps() local
10835 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); in reassociateScalarOps()
10836 return DAG.getNode(Opc, SL, VT, Add1, Op2); in reassociateScalarOps()
10839 static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL, in getMad64_32() argument
10845 SDValue Mad = DAG.getNode(MadOpc, SL, VTs, N0, N1, N2); in getMad64_32()
10846 return DAG.getNode(ISD::TRUNCATE, SL, VT, Mad); in getMad64_32()
10863 SDLoc SL(N); in tryFoldToMad64_32() local
10924 MulLHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, MulLHS); in tryFoldToMad64_32()
10925 MulRHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, MulRHS); in tryFoldToMad64_32()
10926 AddRHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, AddRHS); in tryFoldToMad64_32()
10941 SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in tryFoldToMad64_32()
10942 SDValue One = DAG.getConstant(1, SL, MVT::i32); in tryFoldToMad64_32()
10944 auto MulLHSLo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, MulLHS); in tryFoldToMad64_32()
10945 auto MulRHSLo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, MulRHS); in tryFoldToMad64_32()
10947 getMad64_32(DAG, SL, MVT::i64, MulLHSLo, MulRHSLo, AddRHS, MulSignedLo); in tryFoldToMad64_32()
10950 auto AccumLo = DAG.getNode(ISD::EXTRACT_ELEMENT, SL, MVT::i32, Accum, Zero); in tryFoldToMad64_32()
10951 auto AccumHi = DAG.getNode(ISD::EXTRACT_ELEMENT, SL, MVT::i32, Accum, One); in tryFoldToMad64_32()
10955 DAG.getNode(ISD::EXTRACT_ELEMENT, SL, MVT::i32, MulLHS, One); in tryFoldToMad64_32()
10956 SDValue MulHi = DAG.getNode(ISD::MUL, SL, MVT::i32, MulLHSHi, MulRHSLo); in tryFoldToMad64_32()
10957 AccumHi = DAG.getNode(ISD::ADD, SL, MVT::i32, MulHi, AccumHi); in tryFoldToMad64_32()
10962 DAG.getNode(ISD::EXTRACT_ELEMENT, SL, MVT::i32, MulRHS, One); in tryFoldToMad64_32()
10963 SDValue MulHi = DAG.getNode(ISD::MUL, SL, MVT::i32, MulLHSLo, MulRHSHi); in tryFoldToMad64_32()
10964 AccumHi = DAG.getNode(ISD::ADD, SL, MVT::i32, MulHi, AccumHi); in tryFoldToMad64_32()
10967 Accum = DAG.getBuildVector(MVT::v2i32, SL, {AccumLo, AccumHi}); in tryFoldToMad64_32()
10972 Accum = DAG.getNode(ISD::TRUNCATE, SL, VT, Accum); in tryFoldToMad64_32()
10980 SDLoc SL(N); in performAddCombine() local
11019 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond }; in performAddCombine()
11021 return DAG.getNode(Opc, SL, VTList, Args); in performAddCombine()
11042 SDLoc SL(N); in performSubCombine() local
11060 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond }; in performSubCombine()
11062 return DAG.getNode(Opc, SL, VTList, Args); in performSubCombine()
11110 SDLoc SL(N); in performFAddCombine() local
11123 const SDValue Two = DAG.getConstantFP(2.0, SL, VT); in performFAddCombine()
11124 return DAG.getNode(FusedOp, SL, VT, A, Two, RHS); in performFAddCombine()
11135 const SDValue Two = DAG.getConstantFP(2.0, SL, VT); in performFAddCombine()
11136 return DAG.getNode(FusedOp, SL, VT, A, Two, LHS); in performFAddCombine()
11150 SDLoc SL(N); in performFSubCombine() local
11167 const SDValue Two = DAG.getConstantFP(2.0, SL, VT); in performFSubCombine()
11168 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFSubCombine()
11170 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS); in performFSubCombine()
11182 const SDValue NegTwo = DAG.getConstantFP(-2.0, SL, VT); in performFSubCombine()
11183 return DAG.getNode(FusedOp, SL, VT, A, NegTwo, LHS); in performFSubCombine()
11195 SDLoc SL(N); in performFMACombine() local
11259 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()
11260 DAG.getTargetConstant(0, SL, MVT::i1)); in performFMACombine()
11269 SDLoc SL(N); in performSetCCCombine() local
11296 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
11297 DAG.getConstant(-1, SL, MVT::i1)); in performSetCCCombine()
11322 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
11323 DAG.getConstant(-1, SL, MVT::i1)); in performSetCCCombine()
11354 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
11355 DAG.getConstant(Mask, SL, MVT::i32)); in performSetCCCombine()
11365 SDLoc SL(N); in performCvtF32UByteNCombine() local
11392 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + ShiftOffset / 8, SL, in performCvtF32UByteNCombine()
11411 return DAG.getNode(N->getOpcode(), SL, MVT::f32, DemandedSrc); in performCvtF32UByteNCombine()
11517 SDLoc SL(N); in PerformDAGCombine() local
11521 Src = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Src); in PerformDAGCombine()
11523 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Src); in PerformDAGCombine()
11524 return DAG.getNode(ISD::BITCAST, SL, VT, Ext); in PerformDAGCombine()
11748 SDLoc SL(Node); in legalizeTargetIndependentNode() local
11755 = DAG.getCopyToReg(Node->getOperand(0), SL, VReg, SrcVal, in legalizeTargetIndependentNode()
11758 = DAG.getCopyToReg(ToVReg, SL, SDValue(DestReg, 0), in legalizeTargetIndependentNode()