76 SITargetLowering::SITargetLowering(const TargetMachine &TM,  in SITargetLowering()  function in SITargetLowering
777 const GCNSubtarget *SITargetLowering::getSubtarget() const {  in getSubtarget()
789 bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,  in isFPExtFoldable()
799 bool SITargetLowering::isFPExtFoldable(const MachineInstr &MI, unsigned Opcode,  in isFPExtFoldable()
809 bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {  in isShuffleMaskLegal()
815 MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,  in getRegisterTypeForCallingConv()
841 unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,  in getNumRegistersForCallingConv()
867 unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(  in getVectorTypeBreakdownForCallingConv()
949 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
1171 bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,  in getAddrModeArguments()
1201 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {  in isLegalFlatAddressingMode()
1214 bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {  in isLegalGlobalAddressingMode()
1237 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {  in isLegalMUBUFAddressingMode()
1272 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
1354 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,  in canMergeStoresTo()
1367 bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(  in allowsMisalignedMemoryAccessesImpl()
1518 bool SITargetLowering::allowsMisalignedMemoryAccesses(  in allowsMisalignedMemoryAccesses()
1539 EVT SITargetLowering::getOptimalMemOpType(  in getOptimalMemOpType()
1557 bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {  in isMemOpHasNoClobberedMemOperand()
1562 bool SITargetLowering::isNonGlobalAddrSpace(unsigned AS) {  in isNonGlobalAddrSpace()
1567 bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,  in isFreeAddrSpaceCast()
1579 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {  in isMemOpUniform()
1586 SITargetLowering::getPreferredVectorAction(MVT VT) const {  in getPreferredVectorAction()
1593 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
1599 bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()
1608 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {  in isTypeDesirableForOp()
1634 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,  in lowerKernArgParameterPtr()
1662 SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,  in getImplicitArgPtr()
1669 SDValue SITargetLowering::getLDSKernelId(SelectionDAG &DAG,  in getLDSKernelId()
1680 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,  in convertArgType()
1711 SDValue SITargetLowering::lowerKernargMemParameter(  in lowerKernargMemParameter()
1754 SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,  in lowerStackParameter()
1803 SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,  in getPreloadedValue()
1877 void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,  in allocateSpecialEntryInputVGPRs()
1999 void SITargetLowering::allocateSpecialInputVGPRs(  in allocateSpecialInputVGPRs()
2020 void SITargetLowering::allocateSpecialInputVGPRsFixed(  in allocateSpecialInputVGPRsFixed()
2033 void SITargetLowering::allocateSpecialInputSGPRs(  in allocateSpecialInputSGPRs()
2071 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,  in allocateHSAUserSGPRs()
2132 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,  in allocateSystemSGPRs()
2295 bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {  in supportSplitCSR()
2300 void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {  in initializeSplitCSR()
2304 void SITargetLowering::insertCopiesSplitCSR(  in insertCopiesSplitCSR()
2339 SDValue SITargetLowering::LowerFormalArguments(  in LowerFormalArguments()
2582 bool SITargetLowering::CanLowerReturn(  in CanLowerReturn()
2599 SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
2693 SDValue SITargetLowering::LowerCallResult(  in LowerCallResult()
2751 void SITargetLowering::passSpecialInputs(  in passSpecialInputs()
2959 bool SITargetLowering::isEligibleForTailCallOptimization(  in isEligibleForTailCallOptimization()
3035 bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {  in mayBeEmittedAsTailCall()
3046 SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
3357 SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(  in lowerDYNAMIC_STACKALLOCImpl()
3406 SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
3420 Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,  in getRegisterByName()
3469 SITargetLowering::splitKillBlock(MachineInstr &MI,  in splitKillBlock()
3521 void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {  in bundleInstWithWaitcnt()
3535 SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,  in emitGWSMemViolTestLoop()
3969 MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(  in EmitInstrWithCustomInserter()
4426 bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {  in hasBitPreservingFPLogic()
4430 bool SITargetLowering::hasAtomicFaddRtnForTy(SDValue &Op) const {  in hasAtomicFaddRtnForTy()
4442 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {  in enableAggressiveFMAFusion()
4453 bool SITargetLowering::enableAggressiveFMAFusion(LLT Ty) const { return true; }  in enableAggressiveFMAFusion()
4455 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,  in getSetCCResultType()
4463 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {  in getScalarShiftAmountTy()
4469 LLT SITargetLowering::getPreferredShiftAmountTy(LLT Ty) const {  in getPreferredShiftAmountTy()
4490 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,  in isFMAFasterThanFMulAndFAdd()
4520 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,  in isFMAFasterThanFMulAndFAdd()
4536 bool SITargetLowering::isFMADLegal(const MachineInstr &MI, LLT Ty) const {  in isFMADLegal()
4548 bool SITargetLowering::isFMADLegal(const SelectionDAG &DAG,  in isFMADLegal()
4570 SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,  in splitUnaryVectorOp()
4590 SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,  in splitBinaryVectorOp()
4614 SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,  in splitTernaryVectorOp()
4645 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {  in LowerOperation()
4797 SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,  in adjustLoadValueType()
4834 SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,  in lowerIntrinsicLoad()
4869 static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,  in lowerICMPIntrinsic()
4904 static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,  in lowerFCMPIntrinsic()
4934 static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,  in lowerBALLOTIntrinsic()
4971 void SITargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
5112 unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {  in isCFIntrinsic()
5133 bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {  in shouldEmitFixup()
5140 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {  in shouldEmitGOTReloc()
5149 bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {  in shouldEmitPCReloc()
5153 bool SITargetLowering::shouldUseLDSConstAddress(const GlobalValue *GV) const {  in shouldUseLDSConstAddress()
5163 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,  in LowerBRCOND()
5255 SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,  in LowerRETURNADDR()
5280 SDValue SITargetLowering::getFPExtOrFPRound(SelectionDAG &DAG,  in getFPExtOrFPRound()
5290 SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {  in lowerFP_ROUND()
5306 SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,  in lowerFMINNUM_FMAXNUM()
5325 SDValue SITargetLowering::lowerXMULO(SDValue Op, SelectionDAG &DAG) const {  in lowerXMULO()
5361 SDValue SITargetLowering::lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {  in lowerXMUL_LOHI()
5376 SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {  in lowerTRAP()
5396 SDValue SITargetLowering::lowerTrapEndpgm(  in lowerTrapEndpgm()
5403 SDValue SITargetLowering::loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT,  in loadImplicitKernelArgument()
5414 SDValue SITargetLowering::lowerTrapHsaQueuePtr(  in lowerTrapHsaQueuePtr()
5454 SDValue SITargetLowering::lowerTrapHsa(  in lowerTrapHsa()
5467 SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {  in lowerDEBUGTRAP()
5491 SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,  in getSegmentAperture()
5566 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,  in lowerADDRSPACECAST()
5650 SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,  in lowerINSERT_SUBVECTOR()
5671 SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,  in lowerINSERT_VECTOR_ELT()
5750 SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,  in lowerEXTRACT_VECTOR_ELT()
5844 SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,  in lowerVECTOR_SHUFFLE()
5896 SDValue SITargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,  in lowerSCALAR_TO_VECTOR()
5912 SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,  in lowerBUILD_VECTOR()
5991 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {  in isOffsetFoldingLegal()
6048 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,  in LowerGlobalAddress()
6106 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,  in copyToM0()
6122 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,  in lowerImplicitZextParam()
6322 SDValue SITargetLowering::lowerImage(SDValue Op,  in lowerImage()
6669 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,  in lowerSBuffer()
6751 SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,  in lowerWorkitemID()
6777 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
7138 SDValue SITargetLowering::lowerRawBufferAtomicIntrin(SDValue Op,  in lowerRawBufferAtomicIntrin()
7174 SITargetLowering::lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,  in lowerStructBufferAtomicIntrin()
7200 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,  in LowerINTRINSIC_W_CHAIN()
7863 SDValue SITargetLowering::getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL,  in getMemIntrinsicNode()
7893 SDValue SITargetLowering::handleD16VData(SDValue VData, SelectionDAG &DAG,  in handleD16VData()
7970 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,  in LowerINTRINSIC_VOID()
8401 std::pair<SDValue, SDValue> SITargetLowering::splitBufferOffsets(  in splitBufferOffsets()
8451 void SITargetLowering::setBufferOffsets(SDValue CombinedOffset,  in setBufferOffsets()
8485 SDValue SITargetLowering::handleByteShortBufferLoads(SelectionDAG &DAG,  in handleByteShortBufferLoads()
8504 SDValue SITargetLowering::handleByteShortBufferStores(SelectionDAG &DAG,  in handleByteShortBufferStores()
8540 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const {  in widenLoad()
8607 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {  in LowerLOAD()
8767 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT()
8799 SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,  in lowerFastUnsafeFDIV()
8848 SDValue SITargetLowering::lowerFastUnsafeFDIV64(SDValue Op,  in lowerFastUnsafeFDIV64()
8919 SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV16()
8940 SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {  in lowerFDIV_FAST()
8986 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV32()
9102 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV64()
9169 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV()
9184 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {  in LowerSTORE()
9262 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {  in LowerTrig()
9291 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {  in LowerATOMIC_CMP_SWAP()
9322 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,  in performUCharToFloatCombine()
9370 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,  in performSHLPtrCombine()
9431 SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,  in performMemSDNodeCombine()
9465 SDValue SITargetLowering::splitBinaryBitConstantOp(  in splitBinaryBitConstantOp()
9571 SDValue SITargetLowering::performAndCombine(SDNode *N,  in performAndCombine()
9757 SDValue SITargetLowering::performOrCombine(SDNode *N,  in performOrCombine()
9884 SDValue SITargetLowering::performXorCombine(SDNode *N,  in performXorCombine()
9906 SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,  in performZeroExtendCombine()
9923 SDValue SITargetLowering::performSignExtendInRegCombine(SDNode *N,  in performSignExtendInRegCombine()
9960 SDValue SITargetLowering::performClassCombine(SDNode *N,  in performClassCombine()
9977 SDValue SITargetLowering::performRcpCombine(SDNode *N,  in performRcpCombine()
9999 bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,  in isCanonicalized()
10160 bool SITargetLowering::isCanonicalized(Register Reg, MachineFunction &MF,  in isCanonicalized()
10201 SDValue SITargetLowering::getCanonicalConstantFP(  in getCanonicalConstantFP()
10231 SDValue SITargetLowering::performFCanonicalizeCombine(  in performFCanonicalizeCombine()
10340 SDValue SITargetLowering::performIntMed3ImmCombine(  in performIntMed3ImmCombine()
10394 SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG,  in performFPMed3ImmCombine()
10447 SDValue SITargetLowering::performMinMaxCombine(SDNode *N,  in performMinMaxCombine()
10529 SDValue SITargetLowering::performFMed3Combine(SDNode *N,  in performFMed3Combine()
10573 SDValue SITargetLowering::performCvtPkRTZCombine(SDNode *N,  in performCvtPkRTZCombine()
10584 bool SITargetLowering::shouldExpandVectorDynExt(unsigned EltSize,  in shouldExpandVectorDynExt()
10620 bool SITargetLowering::shouldExpandVectorDynExt(SDNode *N) const {  in shouldExpandVectorDynExt()
10631   return SITargetLowering::shouldExpandVectorDynExt(  in shouldExpandVectorDynExt()
10635 SDValue SITargetLowering::performExtractVectorEltCombine(  in performExtractVectorEltCombine()
10750 SITargetLowering::performInsertVectorEltCombine(SDNode *N,  in performInsertVectorEltCombine()
10778 unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,  in getFusedOpcode()
10804 SDValue SITargetLowering::reassociateScalarOps(SDNode *N,  in reassociateScalarOps()
10857 SDValue SITargetLowering::tryFoldToMad64_32(SDNode *N,  in tryFoldToMad64_32()
10976 SDValue SITargetLowering::performAddCombine(SDNode *N,  in performAddCombine()
11034 SDValue SITargetLowering::performSubCombine(SDNode *N,  in performSubCombine()
11077 SDValue SITargetLowering::performAddCarrySubCarryCombine(SDNode *N,  in performAddCarrySubCarryCombine()
11102 SDValue SITargetLowering::performFAddCombine(SDNode *N,  in performFAddCombine()
11144 SDValue SITargetLowering::performFSubCombine(SDNode *N,  in performFSubCombine()
11191 SDValue SITargetLowering::performFMACombine(SDNode *N,  in performFMACombine()
11266 SDValue SITargetLowering::performSetCCCombine(SDNode *N,  in performSetCCCombine()
11362 SDValue SITargetLowering::performCvtF32UByteNCombine(SDNode *N,  in performCvtF32UByteNCombine()
11416 SDValue SITargetLowering::performClampCombine(SDNode *N,  in performClampCombine()
11438 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
11564 SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,  in adjustWritemask()
11739 SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,  in legalizeTargetIndependentNode()
11784 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,  in PostISelFolding()
11862 void SITargetLowering::AddIMGInit(MachineInstr &MI) const {  in AddIMGInit()
11949 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,  in AdjustInstrPostInstrSelection()
12016 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,  in wrapAddr64Rsrc()
12051 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,  in buildRSRC()
12086 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,  in getRegForInlineAsmConstraint()
12212 SITargetLowering::ConstraintType
12213 SITargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()
12236 void SITargetLowering::LowerAsmOperandForConstraint(SDValue Op,  in LowerAsmOperandForConstraint()
12252 bool SITargetLowering::getAsmOperandConstVal(SDValue Op, uint64_t &Val) const {  in getAsmOperandConstVal()
12286 bool SITargetLowering::checkAsmConstraintVal(SDValue Op,  in checkAsmConstraintVal()
12319 bool SITargetLowering::checkAsmConstraintValA(SDValue Op,  in checkAsmConstraintValA()
12376 void SITargetLowering::finalizeLowering(MachineFunction &MF) const {  in finalizeLowering()
12431 void SITargetLowering::computeKnownBitsForFrameIndex(  in computeKnownBitsForFrameIndex()
12448 void SITargetLowering::computeKnownBitsForTargetInstr(  in computeKnownBitsForTargetInstr()
12490 Align SITargetLowering::computeKnownAlignForTargetInstr(  in computeKnownAlignForTargetInstr()
12511 Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {  in getPrefLoopAlignment()
12599 bool SITargetLowering::isSDNodeSourceOfDivergence(  in isSDNodeSourceOfDivergence()
12666 bool SITargetLowering::denormalsEnabledForType(const SelectionDAG &DAG,  in denormalsEnabledForType()
12679 bool SITargetLowering::denormalsEnabledForType(LLT Ty,  in denormalsEnabledForType()
12692 bool SITargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,  in isKnownNeverNaNForTargetNode()
12720 SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {  in shouldExpandAtomicRMWInIR()
12815 SITargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {  in shouldExpandAtomicLoadInIR()
12822 SITargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {  in shouldExpandAtomicStoreInIR()
12829 SITargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CmpX) const {  in shouldExpandAtomicCmpXchgInIR()
12836 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {  in getRegClassFor()
12902 bool SITargetLowering::requiresUniformRegister(MachineFunction &MF,  in requiresUniformRegister()
12930 SITargetLowering::getTypeLegalizationCost(const DataLayout &DL,  in getTypeLegalizationCost()
12945 bool SITargetLowering::hasMemSDNodeUser(SDNode *N) const {  in hasMemSDNodeUser()
12956 bool SITargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,  in isReassocProfitable()
12970 SITargetLowering::getTargetMMOFlags(const Instruction &I) const {  in getTargetMMOFlags()