Lines Matching refs:MemVT
1354 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo() argument
1357 return (MemVT.getSizeInBits() <= 4 * 32); in canMergeStoresTo()
1360 return (MemVT.getSizeInBits() <= MaxPrivateBits); in canMergeStoresTo()
1362 return (MemVT.getSizeInBits() <= 2 * 32); in canMergeStoresTo()
1680 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT, in convertArgType() argument
1686 VT.getVectorNumElements() != MemVT.getVectorNumElements()) { in convertArgType()
1688 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), in convertArgType()
1696 VT.bitsLT(MemVT)) { in convertArgType()
1698 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT)); in convertArgType()
1701 if (MemVT.isFloatingPoint()) in convertArgType()
1712 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, in lowerKernargMemParameter() argument
1720 if (MemVT.getStoreSize() < 4 && Alignment < 4) { in lowerKernargMemParameter()
1725 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter()
1738 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal); in lowerKernargMemParameter()
1739 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg); in lowerKernargMemParameter()
1746 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment, in lowerKernargMemParameter()
1750 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg); in lowerKernargMemParameter()
1777 MVT MemVT = VA.getValVT(); in lowerStackParameter() local
1783 MemVT = VA.getLocVT(); in lowerStackParameter()
1799 MemVT); in lowerStackParameter()
2458 EVT MemVT = VA.getLocVT(); in LowerFormalArguments() local
2479 DAG, VT, MemVT, DL, Chain, Offset, Alignment, Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
7160 EVT MemVT = VData.getValueType(); in lowerRawBufferAtomicIntrin() local
7161 return DAG.getMemIntrinsicNode(NewOpcode, DL, Op->getVTList(), Ops, MemVT, in lowerRawBufferAtomicIntrin()
7195 EVT MemVT = VData.getValueType(); in lowerStructBufferAtomicIntrin() local
7196 return DAG.getMemIntrinsicNode(NewOpcode, DL, Op->getVTList(), Ops, MemVT, in lowerStructBufferAtomicIntrin()
7865 ArrayRef<SDValue> Ops, EVT MemVT, in getMemIntrinsicNode() argument
7870 EVT WidenedMemVT = MemVT; in getMemIntrinsicNode()
8555 EVT MemVT = Ld->getMemoryVT(); in widenLoad() local
8556 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) || in widenLoad()
8557 MemVT.getSizeInBits() >= 32) in widenLoad()
8562 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && in widenLoad()
8573 EVT TruncVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); in widenLoad()
8574 if (MemVT.isFloatingPoint()) { in widenLoad()
8577 TruncVT = MemVT.changeTypeToInteger(); in widenLoad()
8611 EVT MemVT = Load->getMemoryVT(); in LowerLOAD() local
8613 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) { in LowerLOAD()
8614 if (MemVT == MVT::i16 && isTypeLegal(MVT::i16)) in LowerLOAD()
8624 EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16; in LowerLOAD()
8629 if (!MemVT.isVector()) { in LowerLOAD()
8631 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD), in LowerLOAD()
8639 for (unsigned I = 0, N = MemVT.getVectorNumElements(); I != N; ++I) { in LowerLOAD()
8647 DAG.getBuildVector(MemVT, DL, Elts), in LowerLOAD()
8654 if (!MemVT.isVector()) in LowerLOAD()
8663 Alignment.value() < MemVT.getStoreSize() && MemVT.getSizeInBits() > 32) { in LowerLOAD()
8676 unsigned NumElements = MemVT.getVectorNumElements(); in LowerLOAD()
8681 if (MemVT.isPow2VectorType()) in LowerLOAD()
8697 if (MemVT.isPow2VectorType()) in LowerLOAD()
8748 if (allowsMisalignedMemoryAccessesImpl(MemVT.getSizeInBits(), AS, in LowerLOAD()
8753 if (MemVT.isVector()) in LowerLOAD()
8758 MemVT, *Load->getMemOperand())) { in LowerLOAD()
9372 EVT MemVT, in performSHLPtrCombine() argument
9394 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext()); in performSHLPtrCombine()