Lines Matching refs:INSERT_VECTOR_ELT

254       case ISD::INSERT_VECTOR_ELT:  in SITargetLowering()
283 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
284 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
297 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
298 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v6i32); in SITargetLowering()
311 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
312 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32); in SITargetLowering()
325 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
326 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32); in SITargetLowering()
339 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
340 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32); in SITargetLowering()
354 setOperationAction({ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}, in SITargetLowering()
522 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
629 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec16, Expand); in SITargetLowering()
746 ISD::INSERT_VECTOR_ELT}); in SITargetLowering()
4676 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
4975 case ISD::INSERT_VECTOR_ELT: { in ReplaceNodeResults()
5665 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt, in lowerINSERT_SUBVECTOR()
5698 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16, in lowerINSERT_VECTOR_ELT()
10108 case ISD::INSERT_VECTOR_ELT: { in isCanonicalized()
11531 case ISD::INSERT_VECTOR_ELT: in PerformDAGCombine()