Lines Matching refs:DCI
5761 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in lowerEXTRACT_VECTOR_ELT() local
5767 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI)) in lowerEXTRACT_VECTOR_ELT()
8540 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const { in widenLoad()
8541 SelectionDAG &DAG = DCI.DAG; in widenLoad()
8556 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) || in widenLoad()
8594 DCI.AddToWorklist(Cvt.getNode()); in widenLoad()
8599 DCI.AddToWorklist(Cvt.getNode()); in widenLoad()
9323 DAGCombinerInfo &DCI) const { in performUCharToFloatCombine()
9329 SelectionDAG &DAG = DCI.DAG; in performUCharToFloatCombine()
9339 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
9342 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
9373 DAGCombinerInfo &DCI) const { in performSHLPtrCombine()
9394 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext()); in performSHLPtrCombine()
9399 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace)) in performSHLPtrCombine()
9402 SelectionDAG &DAG = DCI.DAG; in performSHLPtrCombine()
9432 DAGCombinerInfo &DCI) const { in performMemSDNodeCombine()
9433 SelectionDAG &DAG = DCI.DAG; in performMemSDNodeCombine()
9442 N->getMemoryVT(), DCI); in performMemSDNodeCombine()
9466 DAGCombinerInfo &DCI, in splitBinaryBitConstantOp() argument
9481 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi); in splitBinaryBitConstantOp()
9572 DAGCombinerInfo &DCI) const { in performAndCombine()
9573 if (DCI.isBeforeLegalize()) in performAndCombine()
9576 SelectionDAG &DAG = DCI.DAG; in performAndCombine()
9585 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS)) in performAndCombine()
9758 DAGCombinerInfo &DCI) const { in performOrCombine()
9759 SelectionDAG &DAG = DCI.DAG; in performOrCombine()
9843 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
9864 DCI.AddToWorklist(LowOr.getNode()); in performOrCombine()
9865 DCI.AddToWorklist(HiBits.getNode()); in performOrCombine()
9876 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, in performOrCombine()
9885 DAGCombinerInfo &DCI) const { in performXorCombine()
9886 if (SDValue RV = reassociateScalarOps(N, DCI.DAG)) in performXorCombine()
9899 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS)) in performXorCombine()
9907 DAGCombinerInfo &DCI) const { in performZeroExtendCombine()
9909 DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performZeroExtendCombine()
9924 DAGCombinerInfo &DCI) in performSignExtendInRegCombine()
9946 SDVTList ResList = DCI.DAG.getVTList(MVT::i32, in performSignExtendInRegCombine()
9950 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc, SDLoc(N), in performSignExtendInRegCombine()
9954 return DCI.DAG.getMergeValues({BufferLoadSignExt, in performSignExtendInRegCombine()
9961 DAGCombinerInfo &DCI) const { in performClassCombine()
9962 SelectionDAG &DAG = DCI.DAG; in performClassCombine()
9978 DAGCombinerInfo &DCI) const { in performRcpCombine()
9987 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0, in performRcpCombine()
9992 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT, in performRcpCombine()
9996 return AMDGPUTargetLowering::performRcpCombine(N, DCI); in performRcpCombine()
10233 DAGCombinerInfo &DCI) const { in performFCanonicalizeCombine()
10234 SelectionDAG &DAG = DCI.DAG; in performFCanonicalizeCombine()
10310 DCI.AddToWorklist(Canon0.getNode()); in performFCanonicalizeCombine()
10448 DAGCombinerInfo &DCI) const { in performMinMaxCombine()
10449 SelectionDAG &DAG = DCI.DAG; in performMinMaxCombine()
10530 DAGCombinerInfo &DCI) const { in performFMed3Combine()
10535 SelectionDAG &DAG = DCI.DAG; in performFMed3Combine()
10574 DAGCombinerInfo &DCI) const { in performCvtPkRTZCombine()
10578 return DCI.DAG.getUNDEF(N->getValueType(0)); in performCvtPkRTZCombine()
10636 SDNode *N, DAGCombinerInfo &DCI) const { in performExtractVectorEltCombine()
10638 SelectionDAG &DAG = DCI.DAG; in performExtractVectorEltCombine()
10658 if (Vec.hasOneUse() && DCI.isBeforeLegalize()) { in performExtractVectorEltCombine()
10685 DCI.AddToWorklist(Elt0.getNode()); in performExtractVectorEltCombine()
10686 DCI.AddToWorklist(Elt1.getNode()); in performExtractVectorEltCombine()
10711 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
10732 DCI.AddToWorklist(Cast.getNode()); in performExtractVectorEltCombine()
10736 DCI.AddToWorklist(Elt.getNode()); in performExtractVectorEltCombine()
10739 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
10742 DCI.AddToWorklist(Trunc.getNode()); in performExtractVectorEltCombine()
10751 DAGCombinerInfo &DCI) const { in performInsertVectorEltCombine()
10762 SelectionDAG &DAG = DCI.DAG; in performInsertVectorEltCombine()
10858 DAGCombinerInfo &DCI) const { in tryFoldToMad64_32()
10861 SelectionDAG &DAG = DCI.DAG; in tryFoldToMad64_32()
10977 DAGCombinerInfo &DCI) const { in performAddCombine()
10978 SelectionDAG &DAG = DCI.DAG; in performAddCombine()
10986 if (SDValue Folded = tryFoldToMad64_32(N, DCI)) in performAddCombine()
10997 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG()) in performAddCombine()
11035 DAGCombinerInfo &DCI) const { in performSubCombine()
11036 SelectionDAG &DAG = DCI.DAG; in performSubCombine()
11078 DAGCombinerInfo &DCI) const { in performAddCarrySubCarryCombine()
11087 SelectionDAG &DAG = DCI.DAG; in performAddCarrySubCarryCombine()
11103 DAGCombinerInfo &DCI) const { in performFAddCombine()
11104 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performFAddCombine()
11107 SelectionDAG &DAG = DCI.DAG; in performFAddCombine()
11145 DAGCombinerInfo &DCI) const { in performFSubCombine()
11146 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performFSubCombine()
11149 SelectionDAG &DAG = DCI.DAG; in performFSubCombine()
11192 DAGCombinerInfo &DCI) const { in performFMACombine()
11193 SelectionDAG &DAG = DCI.DAG; in performFMACombine()
11267 DAGCombinerInfo &DCI) const { in performSetCCCombine()
11268 SelectionDAG &DAG = DCI.DAG; in performSetCCCombine()
11363 DAGCombinerInfo &DCI) const { in performCvtF32UByteNCombine()
11364 SelectionDAG &DAG = DCI.DAG; in performCvtF32UByteNCombine()
11400 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) { in performCvtF32UByteNCombine()
11404 DCI.AddToWorklist(N); in performCvtF32UByteNCombine()
11417 DAGCombinerInfo &DCI) const { in performClampCombine()
11422 const MachineFunction &MF = DCI.DAG.getMachineFunction(); in performClampCombine()
11427 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0)); in performClampCombine()
11432 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0)); in performClampCombine()
11439 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
11444 return performAddCombine(N, DCI); in PerformDAGCombine()
11446 return performSubCombine(N, DCI); in PerformDAGCombine()
11449 return performAddCarrySubCarryCombine(N, DCI); in PerformDAGCombine()
11451 return performFAddCombine(N, DCI); in PerformDAGCombine()
11453 return performFSubCombine(N, DCI); in PerformDAGCombine()
11455 return performSetCCCombine(N, DCI); in PerformDAGCombine()
11466 return performMinMaxCombine(N, DCI); in PerformDAGCombine()
11468 return performFMACombine(N, DCI); in PerformDAGCombine()
11470 return performAndCombine(N, DCI); in PerformDAGCombine()
11472 return performOrCombine(N, DCI); in PerformDAGCombine()
11474 return performXorCombine(N, DCI); in PerformDAGCombine()
11476 return performZeroExtendCombine(N, DCI); in PerformDAGCombine()
11478 return performSignExtendInRegCombine(N , DCI); in PerformDAGCombine()
11480 return performClassCombine(N, DCI); in PerformDAGCombine()
11482 return performFCanonicalizeCombine(N, DCI); in PerformDAGCombine()
11484 return performRcpCombine(N, DCI); in PerformDAGCombine()
11499 return performUCharToFloatCombine(N, DCI); in PerformDAGCombine()
11504 return performCvtF32UByteNCombine(N, DCI); in PerformDAGCombine()
11506 return performFMed3Combine(N, DCI); in PerformDAGCombine()
11508 return performCvtPkRTZCombine(N, DCI); in PerformDAGCombine()
11510 return performClampCombine(N, DCI); in PerformDAGCombine()
11512 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
11530 return performExtractVectorEltCombine(N, DCI); in PerformDAGCombine()
11532 return performInsertVectorEltCombine(N, DCI); in PerformDAGCombine()
11534 if (SDValue Widended = widenLoad(cast<LoadSDNode>(N), DCI)) in PerformDAGCombine()
11539 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
11541 return performMemSDNodeCombine(MemNode, DCI); in PerformDAGCombine()
11548 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()