Lines Matching refs:R600TargetLowering

29 R600TargetLowering::R600TargetLowering(const TargetMachine &TM,  in R600TargetLowering()  function in R600TargetLowering
210 R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, in EmitInstrWithCustomInserter()
394 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
577 void R600TargetLowering::ReplaceNodeResults(SDNode *N, in ReplaceNodeResults()
619 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG, in vectorToVerticalVector()
634 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, in LowerEXTRACT_VECTOR_ELT()
649 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, in LowerINSERT_VECTOR_ELT()
666 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI, in LowerGlobalAddress()
681 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const { in LowerTrig()
715 SDValue R600TargetLowering::LowerShiftParts(SDValue Op, in LowerShiftParts()
722 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG, in LowerUADDSUBO()
740 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const { in lowerFP_TO_UINT()
750 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const { in lowerFP_TO_SINT()
760 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
775 bool R600TargetLowering::isZero(SDValue Op) const { in isZero()
785 bool R600TargetLowering::isHWTrueValue(SDValue Op) const { in isHWTrueValue()
792 bool R600TargetLowering::isHWFalseValue(SDValue Op) const { in isHWFalseValue()
799 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC()
945 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr, in stackPtrToRegIndex()
967 void R600TargetLowering::getStackAddress(unsigned StackWidth, in getStackAddress()
996 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store, in lowerPrivateTruncStore()
1086 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { in LowerSTORE()
1242 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op, in lowerPrivateExtLoad()
1298 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { in LowerLOAD()
1387 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { in LowerBRCOND()
1396 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op, in lowerFrameIndex()
1411 CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC, in CCAssignFnForCall()
1436 SDValue R600TargetLowering::LowerFormalArguments( in LowerFormalArguments()
1506 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType()
1513 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo()
1522 bool R600TargetLowering::allowsMisalignedMemoryAccesses( in allowsMisalignedMemoryAccesses()
1626 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], in OptimizeSwizzle()
1650 SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block, in constBufferLoad()
1700 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, in PerformDAGCombine()
1927 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, in FoldOperand()
2058 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, in PostISelFolding()