Lines Matching refs:MemVT

1021   EVT MemVT = Store->getMemoryVT();  in lowerPrivateTruncStore()  local
1054 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1095 EVT MemVT = StoreNode->getMemoryVT(); in LowerSTORE() local
1111 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT, in LowerSTORE()
1121 if (Alignment < MemVT.getStoreSize() && in LowerSTORE()
1122 !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment, in LowerSTORE()
1137 if (MemVT == MVT::i8) { in LowerSTORE()
1140 assert(MemVT == MVT::i16); in LowerSTORE()
1168 Op->getVTList(), Args, MemVT, in LowerSTORE()
1187 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1247 EVT MemVT = Load->getMemoryVT(); in lowerPrivateExtLoad() local
1248 assert(Load->getAlignment() >= MemVT.getStoreSize()); in lowerPrivateExtLoad()
1281 EVT MemEltVT = MemVT.getScalarType(); in lowerPrivateExtLoad()
1301 EVT MemVT = LoadNode->getMemoryVT(); in LowerLOAD() local
1305 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1362 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1364 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
1367 DAG.getValueType(MemVT)); in LowerLOAD()
1456 EVT MemVT = VA.getLocVT(); in LowerFormalArguments() local
1457 if (!VT.isVector() && MemVT.isVector()) { in LowerFormalArguments()
1459 MemVT = MemVT.getVectorElementType(); in LowerFormalArguments()
1477 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) { in LowerFormalArguments()
1497 MemVT, Alignment, MachineMemOperand::MONonTemporal | in LowerFormalArguments()
1513 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo() argument
1517 return (MemVT.getSizeInBits() <= 32); in canMergeStoresTo()