Lines Matching refs:DL
427 SDLoc DL(Op); in LowerOperation() local
433 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
434 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
435 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
436 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
438 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
451 SDLoc DL(Op); in LowerOperation() local
468 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
470 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
471 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
472 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
473 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
477 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
478 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
479 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
480 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
488 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
492 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
493 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
495 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
497 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
499 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
501 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
503 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
505 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
507 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
509 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
515 return DAG.getConstant(ByteOffset, DL, PtrVT); in LowerOperation()
518 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
520 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
522 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
524 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
526 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
528 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
530 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
532 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
534 return LowerImplicitParameter(DAG, VT, DL, 8); in LowerOperation()
562 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
565 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
621 SDLoc DL(Vector); in vectorToVerticalVector() local
627 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
628 DAG.getVectorIdxConstant(i, DL))); in vectorToVerticalVector()
631 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
636 SDLoc DL(Op); in LowerEXTRACT_VECTOR_ELT() local
645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
651 SDLoc DL(Op); in LowerINSERT_VECTOR_ELT() local
661 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
673 const DataLayout &DL = DAG.getDataLayout(); in LowerGlobalAddress() local
675 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
686 SDLoc DL(Op); in LowerTrig() local
689 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
690 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
691 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
692 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
693 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
705 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
706 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
707 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
711 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
712 DAG.getConstantFP(numbers::pif, DL, MVT::f32)); in LowerTrig()
724 SDLoc DL(Op); in LowerUADDSUBO() local
730 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
732 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
735 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
737 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
741 SDLoc DL(Op); in lowerFP_TO_UINT() local
744 DL, in lowerFP_TO_UINT()
746 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
751 SDLoc DL(Op); in lowerFP_TO_SINT() local
754 DL, in lowerFP_TO_SINT()
756 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
761 const SDLoc &DL, in LowerImplicitParameter() argument
770 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
771 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
800 SDLoc DL(Op); in LowerSELECT_CC() local
812 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
920 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT); in LowerSELECT_CC()
921 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT); in LowerSELECT_CC()
923 HWTrue = DAG.getConstant(-1, DL, CompareVT); in LowerSELECT_CC()
924 HWFalse = DAG.getConstant(0, DL, CompareVT); in LowerSELECT_CC()
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
934 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
962 SDLoc DL(Ptr); in stackPtrToRegIndex() local
963 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
964 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
998 SDLoc DL(Store); in lowerPrivateTruncStore() local
1007 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1010 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1025 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1030 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1031 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1036 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1041 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1042 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1045 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1046 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1050 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1054 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1057 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1061 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1065 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1068 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1071 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1075 SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo); in lowerPrivateTruncStore()
1080 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1098 SDLoc DL(Op); in LowerSTORE() local
1108 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1111 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT, in LowerSTORE()
1128 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1129 DAG.getConstant(2, DL, PtrVT)); in LowerSTORE()
1138 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1142 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1145 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1146 DAG.getConstant(0x00000003, DL, PtrVT)); in LowerSTORE()
1147 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1148 DAG.getConstant(3, DL, VT)); in LowerSTORE()
1151 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1154 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1155 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1161 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1162 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1165 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1167 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL, in LowerSTORE()
1172 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1177 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1193 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1194 return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1244 SDLoc DL(Op); in lowerPrivateExtLoad() local
1256 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1261 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1262 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1267 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1270 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1271 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1274 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1275 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1278 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1285 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1287 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
1295 return DAG.getMergeValues(Ops, DL); in lowerPrivateExtLoad()
1309 SDLoc DL(Op); in LowerLOAD() local
1319 return DAG.getMergeValues(Ops, DL); in LowerLOAD()
1334 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1335 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1336 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1338 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1343 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1344 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1351 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1364 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
1366 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1370 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1380 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1381 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1382 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1438 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
1464 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
1494 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1495 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1506 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType() argument
1546 SDLoc DL(VectorEntry); in CompactSwizzlableVector() local
1551 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1552 DAG.getIntPtrConstant(i, DL)); in CompactSwizzlableVector()
1590 SDLoc DL(VectorEntry); in ReorganizeVector() local
1596 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1597 DAG.getIntPtrConstant(i, DL)); in ReorganizeVector()
1628 const SDLoc &DL) const { in OptimizeSwizzle()
1636 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1644 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1652 SDLoc DL(LoadNode); in constBufferLoad() local
1674 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1675 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1676 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1684 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements)); in constBufferLoad()
1686 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1687 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1693 return DAG.getMergeValues(MergedValues, DL); in constBufferLoad()
1703 SDLoc DL(N); in PerformDAGCombine() local
1710 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1735 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1738 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1739 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
1786 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1787 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1792 return DAG.getBuildVector(VT, DL, Ops); in PerformDAGCombine()
1811 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
1852 return DAG.getSelectCC(DL, in PerformDAGCombine()
1879 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL); in PerformDAGCombine()
1880 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
1908 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL); in PerformDAGCombine()
1909 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()