Lines Matching refs:STI
50 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
53 printInstruction(MI, Address, STI, OS); in printInst()
58 const MCSubtargetInfo &STI, in printU4ImmOperand() argument
69 const MCSubtargetInfo &STI, in printU16ImmOperand() argument
77 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
96 const MCSubtargetInfo &STI, in printU32ImmOperand() argument
124 const MCSubtargetInfo &STI, in printOffset() argument
134 const MCSubtargetInfo &STI, in printFlatOffset() argument
147 if (AMDGPU::isGFX10(STI)) { in printFlatOffset()
157 const MCSubtargetInfo &STI, in printOffset0() argument
166 const MCSubtargetInfo &STI, in printOffset1() argument
175 const MCSubtargetInfo &STI, in printSMRDOffset8() argument
177 printU32ImmOperand(MI, OpNo, STI, O); in printSMRDOffset8()
181 const MCSubtargetInfo &STI, in printSMEMOffset() argument
187 const MCSubtargetInfo &STI, in printSMEMOffsetMod() argument
190 printSMEMOffset(MI, OpNo, STI, O); in printSMEMOffsetMod()
194 const MCSubtargetInfo &STI, in printSMRDLiteralOffset() argument
196 printU32ImmOperand(MI, OpNo, STI, O); in printSMRDLiteralOffset()
200 const MCSubtargetInfo &STI, raw_ostream &O) { in printGDS() argument
205 const MCSubtargetInfo &STI, raw_ostream &O) { in printCPol() argument
208 O << ((AMDGPU::isGFX940(STI) && in printCPol()
212 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
213 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
215 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
216 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
222 const MCSubtargetInfo &STI, raw_ostream &O) { in printSWZ() argument
226 const MCSubtargetInfo &STI, raw_ostream &O) { in printTFE() argument
231 const MCSubtargetInfo &STI, raw_ostream &O) { in printDMask() argument
234 printU16ImmOperand(MI, OpNo, STI, O); in printDMask()
239 const MCSubtargetInfo &STI, raw_ostream &O) { in printDim() argument
251 const MCSubtargetInfo &STI, raw_ostream &O) { in printUNorm() argument
256 const MCSubtargetInfo &STI, raw_ostream &O) { in printDA() argument
261 const MCSubtargetInfo &STI, raw_ostream &O) { in printR128A16() argument
262 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
269 const MCSubtargetInfo &STI, raw_ostream &O) { in printGFX10A16() argument
274 const MCSubtargetInfo &STI, raw_ostream &O) { in printLWE() argument
279 const MCSubtargetInfo &STI, raw_ostream &O) { in printD16() argument
284 const MCSubtargetInfo &STI, in printExpCompr() argument
290 const MCSubtargetInfo &STI, in printExpVM() argument
296 const MCSubtargetInfo &STI, in printFORMAT() argument
301 const MCSubtargetInfo &STI, in printSymbolicFormat() argument
310 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
313 if (isValidUnifiedFormat(Val, STI)) { in printSymbolicFormat()
314 O << " format:[" << getUnifiedFormatName(Val, STI) << ']'; in printSymbolicFormat()
321 if (isValidDfmtNfmt(Val, STI)) { in printSymbolicFormat()
333 O << getNfmtName(Nfmt, STI); in printSymbolicFormat()
366 const MCSubtargetInfo &STI, raw_ostream &O) { in printVOPDst() argument
385 printRegularOperand(MI, OpNo, STI, O); in printVOPDst()
412 printDefaultVccOperand(false, STI, O); in printVOPDst()
418 const MCSubtargetInfo &STI, raw_ostream &O) { in printVINTRPDst() argument
419 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
424 printRegularOperand(MI, OpNo, STI, O); in printVINTRPDst()
428 const MCSubtargetInfo &STI, in printImmediateInt16() argument
440 const MCSubtargetInfo &STI, in printImmediate16() argument
465 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) { in printImmediate16()
474 const MCSubtargetInfo &STI, in printImmediateV216() argument
477 printImmediate16(Lo16, STI, O); in printImmediateV216()
481 const MCSubtargetInfo &STI, in printImmediate32() argument
508 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in printImmediate32()
515 const MCSubtargetInfo &STI, in printImmediate64() argument
542 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in printImmediate64()
554 const MCSubtargetInfo &STI, in printBLGP() argument
560 if (AMDGPU::isGFX940(STI)) { in printBLGP()
576 const MCSubtargetInfo &STI, in printCBSZ() argument
586 const MCSubtargetInfo &STI, in printABID() argument
596 const MCSubtargetInfo &STI, in printDefaultVccOperand() argument
600 printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] in printDefaultVccOperand()
609 const MCSubtargetInfo &STI, in printWaitVDST() argument
619 const MCSubtargetInfo &STI, in printWaitEXP() argument
638 const MCSubtargetInfo &STI, in printOperand() argument
651 printDefaultVccOperand(true, STI, O); in printOperand()
653 printRegularOperand(MI, OpNo, STI, O); in printOperand()
658 const MCSubtargetInfo &STI, in printRegularOperand() argument
685 printImmediate32(Op.getImm(), STI, O); in printRegularOperand()
692 printImmediate64(Op.getImm(), STI, O); in printRegularOperand()
697 printImmediateInt16(Op.getImm(), STI, O); in printRegularOperand()
703 printImmediate16(Op.getImm(), STI, O); in printRegularOperand()
708 STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { in printRegularOperand()
709 printImmediate32(Op.getImm(), STI, O); in printRegularOperand()
715 printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O); in printRegularOperand()
721 printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O); in printRegularOperand()
725 printImmediateV216(Op.getImm(), STI, O); in printRegularOperand()
751 printImmediate32(FloatToBits(Value), STI, O); in printRegularOperand()
753 printImmediate64(DoubleToBits(Value), STI, O); in printRegularOperand()
797 printDefaultVccOperand(OpNo == 0, STI, O); in printRegularOperand()
806 printSymbolicFormat(MI, STI, O); in printRegularOperand()
812 const MCSubtargetInfo &STI, in printOperandAndFPInputMods() argument
816 printDefaultVccOperand(true, STI, O); in printOperandAndFPInputMods()
840 printRegularOperand(MI, OpNo + 1, STI, O); in printOperandAndFPInputMods()
851 const MCSubtargetInfo &STI, in printOperandAndIntInputMods() argument
855 printDefaultVccOperand(true, STI, O); in printOperandAndIntInputMods()
860 printRegularOperand(MI, OpNo + 1, STI, O); in printOperandAndIntInputMods()
874 printDefaultVccOperand(OpNo == 0, STI, O); in printOperandAndIntInputMods()
880 const MCSubtargetInfo &STI, in printDPP8() argument
882 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
894 const MCSubtargetInfo &STI, in printDPPCtrl() argument
927 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
933 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
939 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
945 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
955 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
961 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
968 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
970 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
980 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
992 const MCSubtargetInfo &STI, in printRowMask() argument
995 printU4ImmOperand(MI, OpNo, STI, O); in printRowMask()
999 const MCSubtargetInfo &STI, in printBankMask() argument
1002 printU4ImmOperand(MI, OpNo, STI, O); in printBankMask()
1006 const MCSubtargetInfo &STI, in printBoundCtrl() argument
1015 const MCSubtargetInfo &STI, in printFI() argument
1042 const MCSubtargetInfo &STI, in printSDWADstSel() argument
1049 const MCSubtargetInfo &STI, in printSDWASrc0Sel() argument
1056 const MCSubtargetInfo &STI, in printSDWASrc1Sel() argument
1063 const MCSubtargetInfo &STI, in printSDWADstUnused() argument
1078 const MCSubtargetInfo &STI, raw_ostream &O, in printExpSrcN() argument
1097 const MCSubtargetInfo &STI, in printExpSrc0() argument
1099 printExpSrcN(MI, OpNo, STI, O, 0); in printExpSrc0()
1103 const MCSubtargetInfo &STI, in printExpSrc1() argument
1105 printExpSrcN(MI, OpNo, STI, O, 1); in printExpSrc1()
1109 const MCSubtargetInfo &STI, in printExpSrc2() argument
1111 printExpSrcN(MI, OpNo, STI, O, 2); in printExpSrc2()
1115 const MCSubtargetInfo &STI, in printExpSrc3() argument
1117 printExpSrcN(MI, OpNo, STI, O, 3); in printExpSrc3()
1121 const MCSubtargetInfo &STI, in printExpTgt() argument
1130 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) { in printExpTgt()
1199 const MCSubtargetInfo &STI, in printOpSel() argument
1217 const MCSubtargetInfo &STI, in printOpSelHi() argument
1223 const MCSubtargetInfo &STI, in printNegLo() argument
1229 const MCSubtargetInfo &STI, in printNegHi() argument
1235 const MCSubtargetInfo &STI, in printInterpSlot() argument
1254 const MCSubtargetInfo &STI, in printInterpAttr() argument
1261 const MCSubtargetInfo &STI, in printInterpAttrChan() argument
1268 const MCSubtargetInfo &STI, in printVGPRIndexMode() argument
1291 const MCSubtargetInfo &STI, in printMemOperand() argument
1293 printRegularOperand(MI, OpNo, STI, O); in printMemOperand()
1295 printRegularOperand(MI, OpNo + 1, STI, O); in printMemOperand()
1319 const MCSubtargetInfo &STI, in printHigh() argument
1325 const MCSubtargetInfo &STI, in printClampSI() argument
1331 const MCSubtargetInfo &STI, in printOModSI() argument
1343 const MCSubtargetInfo &STI, in printSendMsg() argument
1352 decodeMsg(Imm16, MsgId, OpId, StreamId, STI); in printSendMsg()
1354 StringRef MsgName = getMsgName(MsgId, STI); in printSendMsg()
1356 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) && in printSendMsg()
1357 isValidMsgStream(MsgId, OpId, StreamId, STI)) { in printSendMsg()
1359 if (msgRequiresOp(MsgId, STI)) { in printSendMsg()
1360 O << ", " << getMsgOpName(MsgId, OpId, STI); in printSendMsg()
1361 if (msgSupportsStream(MsgId, OpId, STI)) { in printSendMsg()
1407 const MCSubtargetInfo &STI, in printSwizzle() argument
1480 const MCSubtargetInfo &STI, in printWaitFlag() argument
1482 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printWaitFlag()
1515 const MCSubtargetInfo &STI, in printDepCtr() argument
1522 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) { in printDepCtr()
1528 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) { in printDepCtr()
1542 const MCSubtargetInfo &STI, in printDelayFlag() argument
1585 const MCSubtargetInfo &STI, raw_ostream &O) { in printHwreg() argument
1593 StringRef HwRegName = getHwreg(Id, STI); in printHwreg()
1608 const MCSubtargetInfo &STI, in printEndpgm() argument