Lines Matching refs:getNamedOperand
175 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
812 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
876 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
900 if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel)) in checkVALUHazards()
906 !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers) in checkVALUHazards()
912 if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in checkVALUHazards()
969 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
1036 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
1113 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
1191 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); in fixSMEMtoVectorWriteHazards()
1272 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
1380 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVALUHazard()
1413 TII.getNamedOperand(*MI, AMDGPU::OpName::waitvdst); in fixLdsDirectVALUHazard()
1423 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVMEMHazard()
1691 TII->getNamedOperand(*MI, AMDGPU::OpName::src0)->getReg(); in fixWMMAHazards()
1693 TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); in fixWMMAHazards()
1696 TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg(); in fixWMMAHazards()
1706 TII->getNamedOperand(*MI, AMDGPU::OpName::src2); in fixWMMAHazards()
1713 TII->getNamedOperand(*MI, AMDGPU::OpName::src2_modifiers); in fixWMMAHazards()
1748 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in checkNSAtoVMEMHazard()
1970 Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg(); in checkMAIHazards908()
2496 TII.getNamedOperand(MI, AMDGPU::OpName::src2); in checkMAIVALUHazards()