663                     createRegOperand(VAddrRCID, Bytes[i]));  in getInstruction()
742       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),  in convertSDWAInst()
1058 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {  in createRegOperand()  function in AMDGPUDisassembler
1063 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,  in createRegOperand()  function in AMDGPUDisassembler
1069   return createRegOperand(RegCl.getRegister(Val));  in createRegOperand()
1109   return createRegOperand(SRegClassID, Val >> shift);  in createSRegOperand()
1142   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);  in decodeOperand_VGPR_32()
1150   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);  in decodeOperand_AGPR_32()
1154   return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255);  in decodeOperand_AReg_64()
1158   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);  in decodeOperand_AReg_128()
1162   return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255);  in decodeOperand_AReg_256()
1166   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);  in decodeOperand_AReg_512()
1170   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);  in decodeOperand_AReg_1024()
1198   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);  in decodeOperand_VReg_64()
1202   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);  in decodeOperand_VReg_96()
1206   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);  in decodeOperand_VReg_128()
1210   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);  in decodeOperand_VReg_256()
1214   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);  in decodeOperand_VReg_512()
1218   return createRegOperand(AMDGPU::VReg_1024RegClassID, Val);  in decodeOperand_VReg_1024()
1505     return createRegOperand(IsAGPR ? getAgprClassId(Width)  in decodeSrcOp()
1577   return createRegOperand(getVgprClassId(Width), Val);  in decodeVOPDDstYOp()
1584   case 102: return createRegOperand(FLAT_SCR_LO);  in decodeSpecialReg32()
1585   case 103: return createRegOperand(FLAT_SCR_HI);  in decodeSpecialReg32()
1586   case 104: return createRegOperand(XNACK_MASK_LO);  in decodeSpecialReg32()
1587   case 105: return createRegOperand(XNACK_MASK_HI);  in decodeSpecialReg32()
1588   case 106: return createRegOperand(VCC_LO);  in decodeSpecialReg32()
1589   case 107: return createRegOperand(VCC_HI);  in decodeSpecialReg32()
1590   case 108: return createRegOperand(TBA_LO);  in decodeSpecialReg32()
1591   case 109: return createRegOperand(TBA_HI);  in decodeSpecialReg32()
1592   case 110: return createRegOperand(TMA_LO);  in decodeSpecialReg32()
1593   case 111: return createRegOperand(TMA_HI);  in decodeSpecialReg32()
1595     return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);  in decodeSpecialReg32()
1597     return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);  in decodeSpecialReg32()
1598   case 126: return createRegOperand(EXEC_LO);  in decodeSpecialReg32()
1599   case 127: return createRegOperand(EXEC_HI);  in decodeSpecialReg32()
1600   case 235: return createRegOperand(SRC_SHARED_BASE);  in decodeSpecialReg32()
1601   case 236: return createRegOperand(SRC_SHARED_LIMIT);  in decodeSpecialReg32()
1602   case 237: return createRegOperand(SRC_PRIVATE_BASE);  in decodeSpecialReg32()
1603   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);  in decodeSpecialReg32()
1604   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);  in decodeSpecialReg32()
1605   case 251: return createRegOperand(SRC_VCCZ);  in decodeSpecialReg32()
1606   case 252: return createRegOperand(SRC_EXECZ);  in decodeSpecialReg32()
1607   case 253: return createRegOperand(SRC_SCC);  in decodeSpecialReg32()
1608   case 254: return createRegOperand(LDS_DIRECT);  in decodeSpecialReg32()
1618   case 102: return createRegOperand(FLAT_SCR);  in decodeSpecialReg64()
1619   case 104: return createRegOperand(XNACK_MASK);  in decodeSpecialReg64()
1620   case 106: return createRegOperand(VCC);  in decodeSpecialReg64()
1621   case 108: return createRegOperand(TBA);  in decodeSpecialReg64()
1622   case 110: return createRegOperand(TMA);  in decodeSpecialReg64()
1625       return createRegOperand(SGPR_NULL);  in decodeSpecialReg64()
1629       return createRegOperand(SGPR_NULL);  in decodeSpecialReg64()
1631   case 126: return createRegOperand(EXEC);  in decodeSpecialReg64()
1632   case 235: return createRegOperand(SRC_SHARED_BASE);  in decodeSpecialReg64()
1633   case 236: return createRegOperand(SRC_SHARED_LIMIT);  in decodeSpecialReg64()
1634   case 237: return createRegOperand(SRC_PRIVATE_BASE);  in decodeSpecialReg64()
1635   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);  in decodeSpecialReg64()
1636   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);  in decodeSpecialReg64()
1637   case 251: return createRegOperand(SRC_VCCZ);  in decodeSpecialReg64()
1638   case 252: return createRegOperand(SRC_EXECZ);  in decodeSpecialReg64()
1639   case 253: return createRegOperand(SRC_SCC);  in decodeSpecialReg64()
1656       return createRegOperand(getVgprClassId(Width),  in decodeSDWASrc()
1681     return createRegOperand(getVgprClassId(Width), Val);  in decodeSDWASrc()
1717     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);  in decodeSDWAVopcDst()