Lines Matching refs:Val
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, in decodeBoolReg() argument
107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); in decodeBoolReg()
291 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, in decodeOperandVOPDDstY() argument
294 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); in decodeOperandVOPDDstY()
774 unsigned Val = MI.getOperand(OpIdx).getImm(); in collectVOPModifiers() local
776 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; in collectVOPModifiers()
778 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; in collectVOPModifiers()
779 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; in collectVOPModifiers()
780 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; in collectVOPModifiers()
782 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; in collectVOPModifiers()
1064 unsigned Val) const { in createRegOperand()
1066 if (Val >= RegCl.getNumRegs()) in createRegOperand()
1067 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
1068 ": unknown register " + Twine(Val)); in createRegOperand()
1069 return createRegOperand(RegCl.getRegister(Val)); in createRegOperand()
1074 unsigned Val) const { in createSRegOperand()
1104 if (Val % (1 << shift)) { in createSRegOperand()
1106 << ": scalar reg isn't aligned " << Val; in createSRegOperand()
1109 return createRegOperand(SRegClassID, Val >> shift); in createSRegOperand()
1112 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
1113 return decodeSrcOp(OPW32, Val); in decodeOperand_VS_32()
1116 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
1117 return decodeSrcOp(OPW64, Val); in decodeOperand_VS_64()
1120 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { in decodeOperand_VS_128()
1121 return decodeSrcOp(OPW128, Val); in decodeOperand_VS_128()
1124 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { in decodeOperand_VSrc16()
1125 return decodeSrcOp(OPW16, Val); in decodeOperand_VSrc16()
1128 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { in decodeOperand_VSrcV216()
1129 return decodeSrcOp(OPWV216, Val); in decodeOperand_VSrcV216()
1132 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { in decodeOperand_VSrcV232()
1133 return decodeSrcOp(OPWV232, Val); in decodeOperand_VSrcV232()
1136 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
1140 Val &= 255; in decodeOperand_VGPR_32()
1142 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); in decodeOperand_VGPR_32()
1145 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { in decodeOperand_VRegOrLds_32()
1146 return decodeSrcOp(OPW32, Val); in decodeOperand_VRegOrLds_32()
1149 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { in decodeOperand_AGPR_32()
1150 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); in decodeOperand_AGPR_32()
1153 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { in decodeOperand_AReg_64()
1154 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); in decodeOperand_AReg_64()
1157 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { in decodeOperand_AReg_128()
1158 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); in decodeOperand_AReg_128()
1161 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { in decodeOperand_AReg_256()
1162 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); in decodeOperand_AReg_256()
1165 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { in decodeOperand_AReg_512()
1166 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); in decodeOperand_AReg_512()
1169 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { in decodeOperand_AReg_1024()
1170 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); in decodeOperand_AReg_1024()
1173 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { in decodeOperand_AV_32()
1174 return decodeSrcOp(OPW32, Val); in decodeOperand_AV_32()
1177 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { in decodeOperand_AV_64()
1178 return decodeSrcOp(OPW64, Val); in decodeOperand_AV_64()
1181 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { in decodeOperand_AV_128()
1182 return decodeSrcOp(OPW128, Val); in decodeOperand_AV_128()
1185 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { in decodeOperand_AVDst_128()
1187 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. in decodeOperand_AVDst_128()
1188 return decodeSrcOp(OPW128, Val | IS_VGPR); in decodeOperand_AVDst_128()
1191 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { in decodeOperand_AVDst_512()
1193 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. in decodeOperand_AVDst_512()
1194 return decodeSrcOp(OPW512, Val | IS_VGPR); in decodeOperand_AVDst_512()
1197 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { in decodeOperand_VReg_64()
1198 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); in decodeOperand_VReg_64()
1201 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { in decodeOperand_VReg_96()
1202 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); in decodeOperand_VReg_96()
1205 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { in decodeOperand_VReg_128()
1206 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); in decodeOperand_VReg_128()
1209 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { in decodeOperand_VReg_256()
1210 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); in decodeOperand_VReg_256()
1213 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { in decodeOperand_VReg_512()
1214 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); in decodeOperand_VReg_512()
1217 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { in decodeOperand_VReg_1024()
1218 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); in decodeOperand_VReg_1024()
1221 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { in decodeOperand_SReg_32()
1225 return decodeSrcOp(OPW32, Val); in decodeOperand_SReg_32()
1229 unsigned Val) const { in decodeOperand_SReg_32_XM0_XEXEC()
1231 return decodeOperand_SReg_32(Val); in decodeOperand_SReg_32_XM0_XEXEC()
1235 unsigned Val) const { in decodeOperand_SReg_32_XEXEC_HI()
1237 return decodeOperand_SReg_32(Val); in decodeOperand_SReg_32_XEXEC_HI()
1240 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { in decodeOperand_SRegOrLds_32()
1244 return decodeSrcOp(OPW32, Val); in decodeOperand_SRegOrLds_32()
1247 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { in decodeOperand_SReg_64()
1248 return decodeSrcOp(OPW64, Val); in decodeOperand_SReg_64()
1251 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { in decodeOperand_SReg_64_XEXEC()
1252 return decodeSrcOp(OPW64, Val); in decodeOperand_SReg_64_XEXEC()
1255 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { in decodeOperand_SReg_128()
1256 return decodeSrcOp(OPW128, Val); in decodeOperand_SReg_128()
1259 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { in decodeOperand_SReg_256()
1260 return decodeDstOp(OPW256, Val); in decodeOperand_SReg_256()
1263 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { in decodeOperand_SReg_512()
1264 return decodeDstOp(OPW512, Val); in decodeOperand_SReg_512()
1269 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { in decodeMandatoryLiteralConstant()
1274 if (Literal != Val) in decodeMandatoryLiteralConstant()
1275 return errOperand(Val, "More than one unique literal is illegal"); in decodeMandatoryLiteralConstant()
1278 Literal = Val; in decodeMandatoryLiteralConstant()
1486 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { in getTTmpIdx()
1492 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; in getTTmpIdx()
1495 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, in decodeSrcOp() argument
1499 assert(Val < 1024); // enum10 in decodeSrcOp()
1501 bool IsAGPR = Val & 512; in decodeSrcOp()
1502 Val &= 511; in decodeSrcOp()
1504 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { in decodeSrcOp()
1506 : getVgprClassId(Width), Val - VGPR_MIN); in decodeSrcOp()
1508 if (Val <= SGPR_MAX) { in decodeSrcOp()
1511 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); in decodeSrcOp()
1514 int TTmpIdx = getTTmpIdx(Val); in decodeSrcOp()
1519 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) in decodeSrcOp()
1520 return decodeIntImmed(Val); in decodeSrcOp()
1522 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) in decodeSrcOp()
1523 return decodeFPImmed(Width, Val); in decodeSrcOp()
1525 if (Val == LITERAL_CONST) { in decodeSrcOp()
1537 return decodeSpecialReg32(Val); in decodeSrcOp()
1540 return decodeSpecialReg64(Val); in decodeSrcOp()
1546 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { in decodeDstOp()
1549 assert(Val < 128); in decodeDstOp()
1552 if (Val <= SGPR_MAX) { in decodeDstOp()
1555 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); in decodeDstOp()
1558 int TTmpIdx = getTTmpIdx(Val); in decodeDstOp()
1569 unsigned Val) const { in decodeVOPDDstYOp()
1575 Val |= ~XDstReg & 1; in decodeVOPDDstYOp()
1577 return createRegOperand(getVgprClassId(Width), Val); in decodeVOPDDstYOp()
1580 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { in decodeSpecialReg32()
1583 switch (Val) { in decodeSpecialReg32()
1611 return errOperand(Val, "unknown operand encoding " + Twine(Val)); in decodeSpecialReg32()
1614 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { in decodeSpecialReg64()
1617 switch (Val) { in decodeSpecialReg64()
1642 return errOperand(Val, "unknown operand encoding " + Twine(Val)); in decodeSpecialReg64()
1646 const unsigned Val) const { in decodeSDWASrc()
1654 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && in decodeSDWASrc()
1655 Val <= SDWA9EncValues::SRC_VGPR_MAX) { in decodeSDWASrc()
1657 Val - SDWA9EncValues::SRC_VGPR_MIN); in decodeSDWASrc()
1659 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && in decodeSDWASrc()
1660 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 in decodeSDWASrc()
1663 Val - SDWA9EncValues::SRC_SGPR_MIN); in decodeSDWASrc()
1665 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && in decodeSDWASrc()
1666 Val <= SDWA9EncValues::SRC_TTMP_MAX) { in decodeSDWASrc()
1668 Val - SDWA9EncValues::SRC_TTMP_MIN); in decodeSDWASrc()
1671 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; in decodeSDWASrc()
1681 return createRegOperand(getVgprClassId(Width), Val); in decodeSDWASrc()
1686 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { in decodeSDWASrc16()
1687 return decodeSDWASrc(OPW16, Val); in decodeSDWASrc16()
1690 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { in decodeSDWASrc32()
1691 return decodeSDWASrc(OPW32, Val); in decodeSDWASrc32()
1694 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { in decodeSDWAVopcDst()
1703 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { in decodeSDWAVopcDst()
1704 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; in decodeSDWAVopcDst()
1706 int TTmpIdx = getTTmpIdx(Val); in decodeSDWAVopcDst()
1710 } else if (Val > SGPR_MAX) { in decodeSDWAVopcDst()
1711 return IsWave64 ? decodeSpecialReg64(Val) in decodeSDWAVopcDst()
1712 : decodeSpecialReg32(Val); in decodeSDWAVopcDst()
1714 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); in decodeSDWAVopcDst()
1721 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { in decodeBoolReg()
1723 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); in decodeBoolReg()
2135 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { in tryAddingSymbolicOperand() argument
2136 return Val.Addr == static_cast<uint64_t>(Value) && in tryAddingSymbolicOperand()
2137 Val.Type == ELF::STT_NOTYPE; in tryAddingSymbolicOperand()