Lines Matching refs:Operands
1333 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1335 void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
1517 OperandVector &Operands, MCStreamer &Out,
1521 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic,
1525 SMLoc NameLoc, OperandVector &Operands) override;
1531 parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1537 OperandVector &Operands,
1542 parseNamedBit(StringRef Name, OperandVector &Operands,
1544 OperandMatchResultTy parseCPol(OperandVector &Operands);
1555 OperandMatchResultTy parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);
1556 OperandMatchResultTy parseReg(OperandVector &Operands);
1557 OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);
1558 OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm = true);
1559 OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm = true);
1560 OperandMatchResultTy parseRegWithFPInputMods(OperandVector &Operands);
1561 OperandMatchResultTy parseRegWithIntInputMods(OperandVector &Operands);
1562 OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands);
1567 OperandMatchResultTy parseFORMAT(OperandVector &Operands);
1573 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
1574 void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); } in cvtDS() argument
1575 void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); } in cvtDSGds() argument
1576 void cvtExp(MCInst &Inst, const OperandVector &Operands);
1579 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
1583 OperandMatchResultTy parseDepCtrOps(OperandVector &Operands);
1586 OperandMatchResultTy parseSDelayAluOps(OperandVector &Operands);
1588 OperandMatchResultTy parseHwreg(OperandVector &Operands);
1612 SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
1613 SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
1614 SMLoc getBLGPLoc(const OperandVector &Operands) const;
1617 const OperandVector &Operands) const;
1618 SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
1619 SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
1620 SMLoc getLitLoc(const OperandVector &Operands) const;
1621 SMLoc getConstLoc(const OperandVector &Operands) const;
1623 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1624 bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1625 bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
1627 bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
1628 bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector &Operands);
1632 bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
1639 bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
1641 bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
1642 bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
1643 bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
1646 bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
1647 bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
1649 bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
1651 bool validateFlatLdsDMA(const MCInst &Inst, const OperandVector &Operands,
1653 bool validateExeczVcczOperands(const OperandVector &Operands);
1681 bool parseExpr(OperandVector &Operands);
1691 OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
1692 OperandMatchResultTy parseOptionalOpr(OperandVector &Operands);
1694 OperandMatchResultTy parseExpTgt(OperandVector &Operands);
1695 OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
1696 OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
1697 OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
1698 OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
1699 OperandMatchResultTy parseBoolReg(OperandVector &Operands);
1710 OperandMatchResultTy parseSwizzleOp(OperandVector &Operands);
1719 OperandMatchResultTy parseGPRIdxMode(OperandVector &Operands);
1722 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); } in cvtMubuf() argument
1723 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr… in cvtMubufAtomic() argument
1724 …void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false… in cvtMubufLds() argument
1725 void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
1734 OperandMatchResultTy parseOModOperand(OperandVector &Operands);
1736 void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1738 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1739 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1740 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1741 void cvtVOPD(MCInst &Inst, const OperandVector &Operands);
1742 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
1744 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
1747 void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1748 void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1750 void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
1752 void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
1753 void cvtIntersectRay(MCInst &Inst, const OperandVector &Operands);
1755 void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);
1758 OperandMatchResultTy parseDim(OperandVector &Operands);
1759 OperandMatchResultTy parseDPP8(OperandVector &Operands);
1760 OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
1761 bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
1768 void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1769 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { in cvtDPP8() argument
1770 cvtDPP(Inst, Operands, true); in cvtDPP8()
1772 void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
1774 void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3DPP8() argument
1775 cvtVOP3DPP(Inst, Operands, true); in cvtVOP3DPP8()
1778 OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
1780 OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
1781 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1782 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1783 void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1784 void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1785 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1786 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1795 OperandMatchResultTy parseEndpgmOp(OperandVector &Operands);
1800 OperandMatchResultTy parseVOPD(OperandVector &Operands);
2903 AMDGPUAsmParser::parseImm(OperandVector &Operands, bool HasSP3AbsModifier) { in parseImm() argument
2938 Operands.push_back( in parseImm()
2966 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S)); in parseImm()
2968 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S)); in parseImm()
2978 AMDGPUAsmParser::parseReg(OperandVector &Operands) { in parseReg() argument
2984 Operands.push_back(std::move(R)); in parseReg()
2991 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod) { in parseRegOrImm() argument
2992 auto res = parseReg(Operands); in parseRegOrImm()
2998 return parseImm(Operands, HasSP3AbsMod); in parseRegOrImm()
3093 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands, in parseRegOrImmWithFPInputMods() argument
3129 Res = parseRegOrImm(Operands, SP3Abs); in parseRegOrImmWithFPInputMods()
3131 Res = parseReg(Operands); in parseRegOrImmWithFPInputMods()
3149 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); in parseRegOrImmWithFPInputMods()
3160 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands, in parseRegOrImmWithIntInputMods() argument
3168 Res = parseRegOrImm(Operands); in parseRegOrImmWithIntInputMods()
3170 Res = parseReg(Operands); in parseRegOrImmWithIntInputMods()
3183 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); in parseRegOrImmWithIntInputMods()
3195 AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) { in parseRegWithFPInputMods() argument
3196 return parseRegOrImmWithFPInputMods(Operands, false); in parseRegWithFPInputMods()
3200 AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) { in parseRegWithIntInputMods() argument
3201 return parseRegOrImmWithIntInputMods(Operands, false); in parseRegWithIntInputMods()
3204 OperandMatchResultTy AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) { in parseVReg32OrOff() argument
3207 Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc, in parseVReg32OrOff()
3217 Operands.push_back(std::move(Reg)); in parseVReg32OrOff()
3417 const OperandVector &Operands) { in validateConstantBusLimitations() argument
3497 SMLoc LitLoc = getLitLoc(Operands); in validateConstantBusLimitations()
3498 SMLoc RegLoc = getRegLoc(LastSGPR, Operands); in validateConstantBusLimitations()
3506 const OperandVector &Operands) { in validateEarlyClobberLimitations() argument
3534 Error(getRegLoc(SrcReg, Operands), in validateEarlyClobberLimitations()
3725 const OperandVector &Operands) { in validateMovrels() argument
3743 ErrLoc = getRegLoc(Reg, Operands); in validateMovrels()
3745 ErrLoc = getConstLoc(Operands); in validateMovrels()
3753 const OperandVector &Operands) { in validateMAIAccWrite() argument
3770 Error(getRegLoc(Reg, Operands), in validateMAIAccWrite()
3779 const OperandVector &Operands) { in validateMFMA() argument
3804 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands), in validateMFMA()
4037 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const { in getFlatOffsetLoc()
4038 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in getFlatOffsetLoc()
4039 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getFlatOffsetLoc()
4047 const OperandVector &Operands) { in validateFlatOffset() argument
4058 Error(getFlatOffsetLoc(Operands), in validateFlatOffset()
4068 Error(getFlatOffsetLoc(Operands), in validateFlatOffset()
4075 Error(getFlatOffsetLoc(Operands), in validateFlatOffset()
4084 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const { in getSMEMOffsetLoc()
4086 for (unsigned i = 2, e = Operands.size(); i != e; ++i) { in getSMEMOffsetLoc()
4087 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getSMEMOffsetLoc()
4095 const OperandVector &Operands) { in validateSMEMOffset() argument
4118 Error(getSMEMOffsetLoc(Operands), in validateSMEMOffset()
4200 const OperandVector &Operands) { in validateDPP() argument
4212 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands); in validateDPP()
4230 const OperandVector &Operands) { in validateVOPLiteral() argument
4260 Error(getConstLoc(Operands), in validateVOPLiteral()
4281 Error(getLitLoc(Operands), "literal operands are not supported"); in validateVOPLiteral()
4286 Error(getLitLoc(Operands), "only one literal operand is allowed"); in validateVOPLiteral()
4366 SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const { in getBLGPLoc()
4367 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in getBLGPLoc()
4368 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getBLGPLoc()
4376 const OperandVector &Operands) { in validateBLGP() argument
4381 SMLoc BLGPLoc = getBLGPLoc(Operands); in validateBLGP()
4410 const OperandVector &Operands) { in validateGWS() argument
4427 SMLoc RegLoc = getRegLoc(Reg, Operands); in validateGWS()
4436 const OperandVector &Operands, in validateCoherencyBits() argument
4448 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateCoherencyBits()
4459 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateCoherencyBits()
4477 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateCoherencyBits()
4491 const OperandVector &Operands, in validateFlatLdsDMA() argument
4502 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyLDS, Operands); in validateFlatLdsDMA()
4515 bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) { in validateExeczVcczOperands() argument
4518 for (auto &Operand : Operands) { in validateExeczVcczOperands()
4523 Error(getRegLoc(Reg, Operands), in validateExeczVcczOperands()
4533 const OperandVector &Operands) { in validateInstruction() argument
4535 Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg); in validateInstruction()
4539 Error(getLitLoc(Operands), in validateInstruction()
4543 if (!validateVOPLiteral(Inst, Operands)) { in validateInstruction()
4546 if (!validateConstantBusLimitations(Inst, Operands)) { in validateInstruction()
4549 if (!validateEarlyClobberLimitations(Inst, Operands)) { in validateInstruction()
4553 Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands), in validateInstruction()
4558 Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands), in validateInstruction()
4562 if (!validateDPP(Inst, Operands)) { in validateInstruction()
4567 Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands), in validateInstruction()
4576 Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands), in validateInstruction()
4590 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands), in validateInstruction()
4595 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands), in validateInstruction()
4599 if (!validateMovrels(Inst, Operands)) { in validateInstruction()
4602 if (!validateFlatOffset(Inst, Operands)) { in validateInstruction()
4605 if (!validateSMEMOffset(Inst, Operands)) { in validateInstruction()
4608 if (!validateMAIAccWrite(Inst, Operands)) { in validateInstruction()
4611 if (!validateMFMA(Inst, Operands)) { in validateInstruction()
4614 if (!validateCoherencyBits(Inst, Operands, IDLoc)) { in validateInstruction()
4630 if (!validateGWS(Inst, Operands)) { in validateInstruction()
4634 if (!validateBLGP(Inst, Operands)) { in validateInstruction()
4642 if (!validateExeczVcczOperands(Operands)) { in validateInstruction()
4646 if (!validateFlatLdsDMA(Inst, Operands, IDLoc)) { in validateInstruction()
4709 OperandVector &Operands, in MatchAndEmitInstruction() argument
4717 auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm, in MatchAndEmitInstruction()
4738 if (!validateInstruction(Inst, IDLoc, Operands)) { in MatchAndEmitInstruction()
4746 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); in MatchAndEmitInstruction()
4762 if (ErrorInfo >= Operands.size()) { in MatchAndEmitInstruction()
4765 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
5678 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, in parseOperand() argument
5680 OperandMatchResultTy ResTy = parseVOPD(Operands); in parseOperand()
5686 ResTy = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
5701 unsigned Prefix = Operands.size(); in parseOperand()
5705 ResTy = parseReg(Operands); in parseOperand()
5721 if (Operands.size() - Prefix > 1) { in parseOperand()
5722 Operands.insert(Operands.begin() + Prefix, in parseOperand()
5724 Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc)); in parseOperand()
5730 return parseRegOrImm(Operands); in parseOperand()
5765 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
5773 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc)); in ParseInstruction()
5779 if (IsMIMG && isGFX10Plus() && Operands.size() == 2) in ParseInstruction()
5782 OperandMatchResultTy Res = parseOperand(Operands, Name, Mode); in ParseInstruction()
5820 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands, in parseIntWithPrefix() argument
5834 Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy)); in parseIntWithPrefix()
5840 OperandVector &Operands, in parseOperandArrayWithPrefix() argument
5880 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy)); in parseOperandArrayWithPrefix()
5885 AMDGPUAsmParser::parseNamedBit(StringRef Name, OperandVector &Operands, in parseNamedBit() argument
5910 Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy)); in parseNamedBit()
5915 AMDGPUAsmParser::parseCPol(OperandVector &Operands) { in parseCPol() argument
5920 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); in parseCPol()
5973 for (unsigned I = 1; I != Operands.size(); ++I) { in parseCPol()
5974 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in parseCPol()
5981 Operands.push_back(AMDGPUOperand::CreateImm(this, CPolOn, S, in parseCPol()
5988 MCInst& Inst, const OperandVector& Operands, in addOptionalImmOperand() argument
5995 ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1); in addOptionalImmOperand()
6219 AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) { in parseFORMAT() argument
6233 Operands.push_back( in parseFORMAT()
6246 Res = parseRegOrImm(Operands); in parseFORMAT()
6257 auto Size = Operands.size(); in parseFORMAT()
6258 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]); in parseFORMAT()
6277 const OperandVector &Operands) { in cvtDSOffset01() argument
6280 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtDSOffset01()
6281 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtDSOffset01()
6293 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0); in cvtDSOffset01()
6294 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1); in cvtDSOffset01()
6295 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS); in cvtDSOffset01()
6300 void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands, in cvtDSImpl() argument
6305 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtDSImpl()
6306 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtDSImpl()
6326 addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType); in cvtDSImpl()
6329 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS); in cvtDSImpl()
6334 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) { in cvtExp() argument
6341 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtExp()
6342 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtExp()
6389 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM); in cvtExp()
6390 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr); in cvtExp()
6470 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) { in parseSWaitCntOps() argument
6485 Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S)); in parseSWaitCntOps()
6552 AMDGPUAsmParser::parseSDelayAluOps(OperandVector &Operands) { in parseSDelayAluOps() argument
6566 Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S)); in parseSDelayAluOps()
6639 OperandMatchResultTy AMDGPUAsmParser::parseDepCtrOps(OperandVector &Operands) { in parseDepCtrOps() argument
6656 Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc)); in parseDepCtrOps()
6734 AMDGPUAsmParser::parseHwreg(OperandVector &Operands) { in parseHwreg() argument
6759 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg)); in parseHwreg()
6854 AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) { in parseSendMsgOp() argument
6879 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg)); in parseSendMsgOp()
6891 OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) { in parseInterpSlot() argument
6909 Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S, in parseInterpSlot()
6914 OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) { in parseInterpAttr() argument
6953 Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S, in parseInterpAttr()
6955 Operands.push_back(AMDGPUOperand::CreateImm(this, AttrChan, SChan, in parseInterpAttr()
6964 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) { in parseExpTgt() argument
6981 Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S, in parseExpTgt()
7076 AMDGPUAsmParser::parseExpr(OperandVector &Operands) { in parseExpr() argument
7085 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S)); in parseExpr()
7087 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S)); in parseExpr()
7158 const OperandVector &Operands) const { in getOperandLoc()
7159 for (unsigned i = Operands.size() - 1; i > 0; --i) { in getOperandLoc()
7160 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getOperandLoc()
7164 return ((AMDGPUOperand &)*Operands[0]).getStartLoc(); in getOperandLoc()
7169 const OperandVector &Operands) const { in getImmLoc()
7171 return getOperandLoc(Test, Operands); in getImmLoc()
7176 const OperandVector &Operands) const { in getRegLoc()
7180 return getOperandLoc(Test, Operands); in getRegLoc()
7184 AMDGPUAsmParser::getLitLoc(const OperandVector &Operands) const { in getLitLoc()
7188 return getOperandLoc(Test, Operands); in getLitLoc()
7192 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const { in getConstLoc()
7196 return getOperandLoc(Test, Operands); in getConstLoc()
7431 AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) { in parseSwizzleOp() argument
7446 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle)); in parseSwizzleOp()
7452 return parseOptionalOpr(Operands); in parseSwizzleOp()
7510 AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) { in parseGPRIdxMode() argument
7530 Operands.push_back( in parseGPRIdxMode()
7544 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) { in parseSOppBrTarget() argument
7552 if (!parseExpr(Operands)) in parseSOppBrTarget()
7555 AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]); in parseSOppBrTarget()
7575 AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) { in parseBoolReg() argument
7576 return parseReg(Operands); in parseBoolReg()
7588 const OperandVector &Operands, in cvtMubufImpl() argument
7596 for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) { in cvtMubufImpl()
7597 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtMubufImpl()
7614 for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) { in cvtMubufImpl()
7615 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtMubufImpl()
7645 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset); in cvtMubufImpl()
7646 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0); in cvtMubufImpl()
7649 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); in cvtMubufImpl()
7651 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySWZ); in cvtMubufImpl()
7654 void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) { in cvtMtbuf() argument
7657 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtMtbuf()
7658 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtMtbuf()
7683 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtMtbuf()
7685 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyFORMAT); in cvtMtbuf()
7686 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0); in cvtMtbuf()
7687 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); in cvtMtbuf()
7688 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySWZ); in cvtMtbuf()
7695 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands, in cvtMIMG() argument
7700 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtMIMG()
7706 ((AMDGPUOperand &)*Operands[I - 1]).addRegOperands(Inst, 1); in cvtMIMG()
7711 for (unsigned E = Operands.size(); I != E; ++I) { in cvtMIMG()
7712 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtMIMG()
7726 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask); in cvtMIMG()
7728 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDim, -1); in cvtMIMG()
7729 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm); in cvtMIMG()
7730 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol); in cvtMIMG()
7731 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16); in cvtMIMG()
7733 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16); in cvtMIMG()
7735 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); in cvtMIMG()
7736 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE); in cvtMIMG()
7738 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA); in cvtMIMG()
7739 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16); in cvtMIMG()
7742 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) { in cvtMIMGAtomic() argument
7743 cvtMIMG(Inst, Operands, true); in cvtMIMGAtomic()
7746 void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) { in cvtSMEMAtomic() argument
7750 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtSMEMAtomic()
7751 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtSMEMAtomic()
7767 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtSMEMAtomic()
7768 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtSMEMAtomic()
7797 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset); in cvtSMEMAtomic()
7798 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0); in cvtSMEMAtomic()
7802 const OperandVector &Operands) { in cvtIntersectRay() argument
7803 for (unsigned I = 1; I < Operands.size(); ++I) { in cvtIntersectRay()
7804 auto &Operand = (AMDGPUOperand &)*Operands[I]; in cvtIntersectRay()
7945 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) { in parseOptionalOperand() argument
7947 OperandMatchResultTy res = parseOptionalOpr(Operands); in parseOptionalOperand()
7966 res = parseOptionalOpr(Operands); in parseOptionalOperand()
7972 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands) { in parseOptionalOpr() argument
7977 res = parseNamedBit(Op.Name, Operands, Op.Type); in parseOptionalOpr()
7979 res = parseOModOperand(Operands); in parseOptionalOpr()
7983 res = parseSDWASel(Operands, Op.Name, Op.Type); in parseOptionalOpr()
7985 res = parseSDWADstUnused(Operands); in parseOptionalOpr()
7990 res = parseOperandArrayWithPrefix(Op.Name, Operands, Op.Type, in parseOptionalOpr()
7993 res = parseDim(Operands); in parseOptionalOpr()
7995 res = parseCPol(Operands); in parseOptionalOpr()
7997 res = parseDPP8(Operands); in parseOptionalOpr()
7999 res = parseDPPCtrl(Operands); in parseOptionalOpr()
8001 res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult); in parseOptionalOpr()
8003 res = parseOperandArrayWithPrefix("neg", Operands, in parseOptionalOpr()
8015 OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) { in parseOModOperand() argument
8018 return parseIntWithPrefix("mul", Operands, in parseOModOperand()
8023 return parseIntWithPrefix("div", Operands, in parseOModOperand()
8057 const OperandVector &Operands) { in cvtVOP3OpSel() argument
8058 cvtVOP3P(Inst, Operands); in cvtVOP3OpSel()
8062 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands, in cvtVOP3OpSel() argument
8064 cvtVOP3P(Inst, Operands, OptionalIdx); in cvtVOP3OpSel()
8079 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) in cvtVOP3Interp() argument
8087 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3Interp()
8090 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3Interp()
8091 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3Interp()
8106 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh); in cvtVOP3Interp()
8110 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); in cvtVOP3Interp()
8114 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI); in cvtVOP3Interp()
8118 void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands) in cvtVINTERP() argument
8126 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVINTERP()
8129 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVINTERP()
8130 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVINTERP()
8140 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); in cvtVINTERP()
8144 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel); in cvtVINTERP()
8146 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP); in cvtVINTERP()
8178 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands, in cvtVOP3() argument
8185 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3()
8190 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3()
8191 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3()
8204 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3()
8205 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3()
8215 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); in cvtVOP3()
8219 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI); in cvtVOP3()
8249 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3() argument
8251 cvtVOP3(Inst, Operands, OptionalIdx); in cvtVOP3()
8254 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, in cvtVOP3P() argument
8277 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel); in cvtVOP3P()
8283 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, in cvtVOP3P()
8289 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo); in cvtVOP3P()
8290 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi); in cvtVOP3P()
8345 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3P() argument
8347 cvtVOP3(Inst, Operands, OptIdx); in cvtVOP3P()
8348 cvtVOP3P(Inst, Operands, OptIdx); in cvtVOP3P()
8355 OperandMatchResultTy AMDGPUAsmParser::parseVOPD(OperandVector &Operands) { in parseVOPD() argument
8363 Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S)); in parseVOPD()
8366 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S)); in parseVOPD()
8384 void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) { in cvtVOPD() argument
8386 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtVOPD()
8552 OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) { in parseDim() argument
8568 Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S, in parseDim()
8577 OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) { in parseDPP8() argument
8610 Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8)); in parseDPP8()
8616 const OperandVector &Operands) { in isSupportedDPPCtrl() argument
8718 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { in parseDPPCtrl() argument
8722 !isSupportedDPPCtrl(getTokenStr(), Operands)) in parseDPPCtrl()
8748 Operands.push_back( in parseDPPCtrl()
8773 void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) { in cvtVOP3DPP() argument
8780 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3DPP()
8784 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3DPP()
8792 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3DPP()
8813 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); in cvtVOP3DPP()
8816 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI); in cvtVOP3DPP()
8819 cvtVOP3P(Inst, Operands, OptionalIdx); in cvtVOP3DPP()
8821 cvtVOP3OpSel(Inst, Operands, OptionalIdx); in cvtVOP3DPP()
8823 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel); in cvtVOP3DPP()
8827 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8); in cvtVOP3DPP()
8831 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4); in cvtVOP3DPP()
8832 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf); in cvtVOP3DPP()
8833 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf); in cvtVOP3DPP()
8834 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl); in cvtVOP3DPP()
8836 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi); in cvtVOP3DPP()
8841 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) { in cvtDPP() argument
8850 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtDPP()
8854 for (unsigned E = Operands.size(); I != E; ++I) { in cvtDPP()
8862 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtDPP()
8904 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf); in cvtDPP()
8905 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf); in cvtDPP()
8906 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl); in cvtDPP()
8908 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi); in cvtDPP()
8918 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix, in parseSDWASel() argument
8948 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type)); in parseSDWASel()
8953 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { in parseSDWADstUnused() argument
8978 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySdwaDstUnused)); in parseSDWADstUnused()
8982 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP1() argument
8983 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1); in cvtSdwaVOP1()
8986 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP2() argument
8987 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
8990 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP2b() argument
8991 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true); in cvtSdwaVOP2b()
8994 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP2e() argument
8995 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true); in cvtSdwaVOP2e()
8998 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOPC() argument
8999 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()
9002 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands, in cvtSDWA() argument
9015 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtSDWA()
9018 for (unsigned E = Operands.size(); I != E; ++I) { in cvtSDWA()
9019 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtSDWA()
9057 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9062 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9067 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9072 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9076 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD… in cvtSDWA()
9080 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0); in cvtSDWA()
9082 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0); in cvtSDWA()
9084 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD); in cvtSDWA()
9085 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::U… in cvtSDWA()
9086 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD… in cvtSDWA()
9087 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD… in cvtSDWA()
9092 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0); in cvtSDWA()
9093 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD… in cvtSDWA()
9094 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD… in cvtSDWA()
9200 OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) { in parseEndpgmOp() argument
9214 Operands.push_back( in parseEndpgmOp()