Lines Matching refs:getOptLevel

565   bool EnableOpt = getOptLevel() > CodeGenOpt::None;  in adjustPassManager()
571 EnablePromoteKernelArguments && getOptLevel() > CodeGenOpt::Less; in adjustPassManager()
899 return getStandardCSEConfigForOpt(TM->getOptLevel()); in getCSEConfig()
979 if (getOptLevel() == CodeGenOpt::Aggressive) in addEarlyCSEOrGVNPass()
1046 if (TM.getOptLevel() > CodeGenOpt::None) in addIRPasses()
1051 if (TM.getOptLevel() > CodeGenOpt::None) { in addIRPasses()
1118 if (TM->getOptLevel() > CodeGenOpt::None) in addPreISel()
1124 addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel())); in addInstSelector()
1158 if (TM->getOptLevel() > CodeGenOpt::None) in addPreISel()
1165 if (TM->getOptLevel() > CodeGenOpt::None) in addPreISel()
1184 if (TM->getOptLevel() > CodeGenOpt::Less) in addPreISel()
1230 addPass(new IRTranslator(getOptLevel())); in addIRTranslator()
1235 bool IsOptNone = getOptLevel() == CodeGenOpt::None; in addPreLegalizeMachineIR()
1246 bool IsOptNone = getOptLevel() == CodeGenOpt::None; in addPreRegBankSelect()
1256 bool IsOptNone = getOptLevel() == CodeGenOpt::None; in addPreGlobalInstructionSelect()
1261 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
1300 if (TM->getOptLevel() > CodeGenOpt::Less) in addOptimizedRegAlloc()
1401 if (getOptLevel() > CodeGenOpt::None) in addPostRegAlloc()
1407 if (TM->getOptLevel() > CodeGenOpt::None) in addPreSched2()
1420 if (getOptLevel() > CodeGenOpt::None) in addPreEmitPass()
1426 if (getOptLevel() > CodeGenOpt::None) in addPreEmitPass()
1438 if (getOptLevel() > CodeGenOpt::Less) in addPreEmitPass()