151       const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);  in applyBank()  local
152       assert(DstBank != &AMDGPU::VCCRegBank);  in applyBank()
1057   const RegisterBank *DstBank =  in applyMappingLoad()  local
1059   if (DstBank == &AMDGPU::SGPRRegBank) {  in applyMappingLoad()
1100         ApplyRegBankMapping ApplyBank(*this, MRI, DstBank);  in applyMappingLoad()
1469   const RegisterBank *DstBank =  in applyMappingBFE()  local
1471   if (DstBank == &AMDGPU::VGPRRegBank) {  in applyMappingBFE()
1628   const RegisterBank &DstBank =  in applyMappingMAD_64_32()  local
1660     MRI.setRegBank(Src2Lo, DstBank);  in applyMappingMAD_64_32()
1661     MRI.setRegBank(Src2Hi, DstBank);  in applyMappingMAD_64_32()
1674     MRI.setRegBank(DstLo, DstBank);  in applyMappingMAD_64_32()
1679     MRI.setRegBank(DstHi, DstBank);  in applyMappingMAD_64_32()
1948   const RegisterBank &DstBank =  in foldExtractEltToCmpSelect()  local
1954     (DstBank == AMDGPU::SGPRRegBank &&  in foldExtractEltToCmpSelect()
1989         MRI.setRegBank(S->getOperand(N).getReg(), DstBank);  in foldExtractEltToCmpSelect()
1998     MRI.setRegBank(DstReg, DstBank);  in foldExtractEltToCmpSelect()
2001   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);  in foldExtractEltToCmpSelect()
2046   const RegisterBank &DstBank =  in foldInsertEltToCmpSelect()  local
2054     (DstBank == AMDGPU::SGPRRegBank &&  in foldInsertEltToCmpSelect()
2086       Register Op0 = constrainRegToBank(MRI, B, InsRegs[L], DstBank);  in foldInsertEltToCmpSelect()
2088       Op1 = constrainRegToBank(MRI, B, Op1, DstBank);  in foldInsertEltToCmpSelect()
2091       MRI.setRegBank(Select, DstBank);  in foldInsertEltToCmpSelect()
2102     MRI.setRegBank(Vec->getOperand(0).getReg(), DstBank);  in foldInsertEltToCmpSelect()
2106   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);  in foldInsertEltToCmpSelect()
2125     const RegisterBank *DstBank =  in applyMappingImpl()  local
2127     if (DstBank == &AMDGPU::VCCRegBank) {  in applyMappingImpl()
2158     ApplyRegBankMapping ApplyBank(*this, MRI, DstBank);  in applyMappingImpl()
2177     const RegisterBank *DstBank =  in applyMappingImpl()  local
2179     if (DstBank != &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2296       const RegisterBank *DstBank =  in applyMappingImpl()  local
2298       if (DstBank == &AMDGPU::VCCRegBank)  in applyMappingImpl()
2302       ApplyRegBankMapping ApplyBank(*this, MRI, DstBank);  in applyMappingImpl()
2390     const RegisterBank *DstBank =  in applyMappingImpl()  local
2392     if (DstBank == &AMDGPU::VGPRRegBank)  in applyMappingImpl()
2471     const RegisterBank *DstBank =  in applyMappingImpl()  local
2473     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2496     const RegisterBank *DstBank =  in applyMappingImpl()  local
2498     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2583       const RegisterBank *DstBank = &AMDGPU::VGPRRegBank;  in applyMappingImpl()  local
2595       MRI.setRegBank(True.getReg(0), *DstBank);  in applyMappingImpl()
2596       MRI.setRegBank(False.getReg(0), *DstBank);  in applyMappingImpl()
2597       MRI.setRegBank(DstReg, *DstBank);  in applyMappingImpl()
2604         MRI.setRegBank(Sel.getReg(0), *DstBank);  in applyMappingImpl()
2627     const RegisterBank *DstBank =  in applyMappingImpl()  local
2629     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2673     MRI.setRegBank(Or.getReg(0), *DstBank);  in applyMappingImpl()
2698     const RegisterBank *DstBank = DstMapping.BreakDown[0].RegBank;  in applyMappingImpl()  local
2725     const bool NeedCopyToVGPR = DstBank == &AMDGPU::VGPRRegBank &&  in applyMappingImpl()
2772     MRI.setRegBank(DstReg, *DstBank);  in applyMappingImpl()
2888     const RegisterBank *DstBank =  in applyMappingImpl()  local
2897     MRI.setRegBank(InsLo.getReg(0), *DstBank);  in applyMappingImpl()
2898     MRI.setRegBank(InsHi.getReg(0), *DstBank);  in applyMappingImpl()
3562     const RegisterBank *DstBank = getRegBank(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()  local
3567     if (!DstBank)  in getInstrMapping()
3568       DstBank = SrcBank;  in getInstrMapping()
3571     if (cannotCopy(*DstBank, *SrcBank, Size))  in getInstrMapping()
3574     const ValueMapping &ValMap = getValueMapping(0, Size, *DstBank);  in getInstrMapping()
3617     if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))  in getInstrMapping()  local
3618       ResultBank = DstBank->getID();  in getInstrMapping()
3661       const RegisterBank *DstBank  in getInstrMapping()  local
3667       if (DstBank) {  in getInstrMapping()
3668         TargetBankID = DstBank->getID();  in getInstrMapping()
3669         if (DstBank == &AMDGPU::VCCRegBank) {  in getInstrMapping()
3974     unsigned DstBank;  in getInstrMapping()  local
3979       DstBank = AMDGPU::SGPRRegBankID;  in getInstrMapping()
3982       DstBank = AMDGPU::VGPRRegBankID;  in getInstrMapping()
3988     OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);  in getInstrMapping()
4019     unsigned DstBank = getRegBankID(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()  local
4024     bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID &&  in getInstrMapping()
4031     DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;  in getInstrMapping()
4038     OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize);  in getInstrMapping()