Lines Matching refs:VOffset
3042 MachineOperand &VOffset = MI.getOperand(4); in selectAMDGPU_BUFFER_ATOMIC_FADD() local
3046 bool HasVOffset = !isOperandImmEqual(VOffset, 0, *MRI); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3084 .addReg(VOffset.getReg()) in selectAMDGPU_BUFFER_ATOMIC_FADD()
3091 I.add(VOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3158 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in selectBufferLoadLds() local
3160 getIConstantVRegValWithLookThrough(VOffset, *MRI); in selectBufferLoadLds()
3198 .addReg(VOffset) in selectBufferLoadLds()
3205 MIB.addReg(VOffset); in selectBufferLoadLds()
3281 Register VOffset; in selectGlobalLoadLds() local
3295 VOffset = Off; in selectGlobalLoadLds()
3303 if (!VOffset) { in selectGlobalLoadLds()
3304 VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalLoadLds()
3305 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_MOV_B32_e32), VOffset) in selectGlobalLoadLds()
3314 MIB.addReg(VOffset); in selectGlobalLoadLds()
4088 if (Register VOffset = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) { in selectGlobalSAddr() local
4093 MIB.addReg(VOffset); in selectGlobalSAddr()
4112 Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalSAddr() local
4114 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32), VOffset) in selectGlobalSAddr()
4119 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()