Lines Matching refs:MIB
544 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
548 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
549 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
692 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR_TRUNC() local
697 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC()
803 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
808 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_SBFX_UBFX()
873 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_WRITELANE_B32), VDst); in selectWritelane() local
880 MIB.addReg(Val); in selectWritelane()
881 MIB.addImm(ConstSelect->Value.getSExtValue() & in selectWritelane()
891 MIB.addImm(ConstVal->Value.getSExtValue()); in selectWritelane()
892 MIB.addReg(LaneSelect); in selectWritelane()
894 MIB.addReg(Val); in selectWritelane()
901 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectWritelane()
903 MIB.addReg(AMDGPU::M0); in selectWritelane()
907 MIB.addReg(VDstIn); in selectWritelane()
910 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectWritelane()
939 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0) in selectDivScale() local
951 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDivScale()
1244 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg); in selectGroupStaticSize() local
1248 MIB.addImm(MFI->getLDSSize()); in selectGroupStaticSize()
1253 MIB.addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO); in selectGroupStaticSize()
1257 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGroupStaticSize()
1469 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID))); in selectDSGWSIntrinsic() local
1473 MIB.addReg(VSrc); in selectDSGWSIntrinsic()
1479 MIB.addImm(ImmOffset) in selectDSGWSIntrinsic()
1482 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::data0); in selectDSGWSIntrinsic()
1512 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg()) in selectDSAppendConsume() local
1517 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDSAppendConsume()
1706 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode)) in selectImageIntrinsic() local
1717 MIB.addDef(TmpReg); in selectImageIntrinsic()
1724 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
1729 MIB.addReg(VDataIn); // vdata input in selectImageIntrinsic()
1735 MIB.addReg(SrcOp.getReg()); in selectImageIntrinsic()
1739 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
1741 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg()); in selectImageIntrinsic()
1743 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
1746 MIB.addImm(DimInfo->Encoding); in selectImageIntrinsic()
1747 MIB.addImm(Unorm); in selectImageIntrinsic()
1749 MIB.addImm(CPol); in selectImageIntrinsic()
1750 MIB.addImm(IsA16 && // a16 or r128 in selectImageIntrinsic()
1753 MIB.addImm(IsA16 ? -1 : 0); in selectImageIntrinsic()
1756 MIB.addImm(TFE); // tfe in selectImageIntrinsic()
1762 MIB.addImm(LWE); // lwe in selectImageIntrinsic()
1764 MIB.addImm(DimInfo->DA ? -1 : 0); in selectImageIntrinsic()
1766 MIB.addImm(IsD16 ? -1 : 0); in selectImageIntrinsic()
1775 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::V_MOV_B32_e32), Zero) in selectImageIntrinsic()
1782 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), Tied); in selectImageIntrinsic()
1789 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef); in selectImageIntrinsic()
1791 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), Tied); in selectImageIntrinsic()
1796 MIB.addReg(Tied, RegState::Implicit); in selectImageIntrinsic()
1797 MIB->tieOperands(0, MIB->getNumOperands() - 1); in selectImageIntrinsic()
1801 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectImageIntrinsic()
1802 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::vaddr); in selectImageIntrinsic()
2573 auto MIB = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_AND_B64), DstReg) in selectG_PTRMASK() local
2577 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_PTRMASK()
3134 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)) in selectGlobalAtomicFadd() local
3142 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobalAtomicFadd()
3191 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)); in selectBufferLoadLds() local
3195 BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg) in selectBufferLoadLds()
3201 MIB.addReg(IdxReg); in selectBufferLoadLds()
3203 MIB.addReg(VIndex); in selectBufferLoadLds()
3205 MIB.addReg(VOffset); in selectBufferLoadLds()
3208 MIB.add(MI.getOperand(1)); // rsrc in selectBufferLoadLds()
3209 MIB.add(MI.getOperand(5 + OpOffset)); // soffset in selectBufferLoadLds()
3210 MIB.add(MI.getOperand(6 + OpOffset)); // imm offset in selectBufferLoadLds()
3212 MIB.addImm(Aux & AMDGPU::CPol::ALL); // cpol in selectBufferLoadLds()
3213 MIB.addImm((Aux >> 3) & 1); // swz in selectBufferLoadLds()
3231 MIB.setMemRefs({LoadMMO, StoreMMO}); in selectBufferLoadLds()
3234 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectBufferLoadLds()
3310 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)) in selectGlobalLoadLds() local
3314 MIB.addReg(VOffset); in selectGlobalLoadLds()
3316 MIB.add(MI.getOperand(4)) // offset in selectGlobalLoadLds()
3333 MIB.setMemRefs({LoadMMO, StoreMMO}); in selectGlobalLoadLds()
3336 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobalLoadLds()
3575 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
3624 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
3635 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods0()
3636 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3Mods0()
3637 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3Mods0()
3638 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3Mods0()
3649 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3BMods0()
3650 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3BMods0()
3651 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3BMods0()
3652 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3BMods0()
3659 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectVOP3OMods()
3660 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3OMods()
3661 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3OMods()
3672 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods()
3673 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods()
3684 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3BMods()
3685 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3BMods()
3697 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3735 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3736 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMods()
3750 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
3751 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PModsDOT()
3766 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectDotIUVOP3PMods()
3780 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectWMMAOpSelVOP3PMods()
3793 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods_nnan()
3794 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods_nnan()
3802 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, in selectVOP3OpSelMods()
3803 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods in selectVOP3OpSelMods()
3817 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVINTERPMods()
3818 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPMods()
3832 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVINTERPModsHi()
3833 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPModsHi()
3911 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdImm()
3912 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdImm()
3931 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
3932 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } in selectSmrdImm32()
3942 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgpr()
3943 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectSmrdSgpr()
3953 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgprImm()
3954 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSmrdSgprImm()
3955 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdSgprImm()
3987 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
3988 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectFlatOffset()
3997 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
3998 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectGlobalOffset()
4007 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
4008 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectScratchOffset()
4053 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
4054 [=](MachineInstrBuilder &MIB) { in selectGlobalSAddr()
4055 MIB.addReg(HighBits); in selectGlobalSAddr()
4057 [=](MachineInstrBuilder &MIB) { MIB.addImm(SplitImmOffset); }, in selectGlobalSAddr()
4089 return {{[=](MachineInstrBuilder &MIB) { // saddr in selectGlobalSAddr()
4090 MIB.addReg(SAddr); in selectGlobalSAddr()
4092 [=](MachineInstrBuilder &MIB) { // voffset in selectGlobalSAddr()
4093 MIB.addReg(VOffset); in selectGlobalSAddr()
4095 [=](MachineInstrBuilder &MIB) { // offset in selectGlobalSAddr()
4096 MIB.addImm(ImmOffset); in selectGlobalSAddr()
4118 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
4119 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
4120 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectGlobalSAddr()
4146 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSAddr()
4147 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
4177 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
4178 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
4234 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4235 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSVAddr()
4236 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
4244 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4245 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr in selectScratchSVAddr()
4246 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
4268 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
4269 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4271 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
4272 MIB.addReg(HighBits); in selectMUBUFScratchOffen()
4274 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
4277 MIB.addImm(0); in selectMUBUFScratchOffen()
4279 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
4280 MIB.addImm(Offset & 4095); in selectMUBUFScratchOffen()
4310 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
4311 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4313 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
4315 MIB.addFrameIndex(FI.value()); in selectMUBUFScratchOffen()
4317 MIB.addReg(VAddr); in selectMUBUFScratchOffen()
4319 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
4322 MIB.addImm(0); in selectMUBUFScratchOffen()
4324 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
4325 MIB.addImm(Offset); in selectMUBUFScratchOffen()
4390 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4391 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4393 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4394 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4396 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // offset in selectMUBUFScratchOffset()
4413 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4414 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4416 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4417 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4419 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
4428 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4429 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4431 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4432 MIB.addImm(0); in selectMUBUFScratchOffset()
4434 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
4474 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
4475 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } in selectDS1Addr1Offset()
4496 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
4497 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, in selectDSReadWrite2()
4498 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); } in selectDSReadWrite2()
4553 static void addZeroImm(MachineInstrBuilder &MIB) { in addZeroImm() argument
4554 MIB.addImm(0); in addZeroImm()
4767 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFAddr64()
4768 MIB.addReg(RSrcReg); in selectMUBUFAddr64()
4770 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFAddr64()
4771 MIB.addReg(VAddr); in selectMUBUFAddr64()
4773 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFAddr64()
4775 MIB.addReg(SOffset); in selectMUBUFAddr64()
4777 MIB.addImm(0); in selectMUBUFAddr64()
4779 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFAddr64()
4780 MIB.addImm(Offset); in selectMUBUFAddr64()
4798 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFOffset()
4799 MIB.addReg(RSrcReg); in selectMUBUFOffset()
4801 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFOffset()
4803 MIB.addReg(SOffset); in selectMUBUFOffset()
4805 MIB.addImm(0); in selectMUBUFOffset()
4807 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffset()
4827 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFAddr64Atomic()
4828 MIB.addReg(RSrcReg); in selectMUBUFAddr64Atomic()
4830 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFAddr64Atomic()
4831 MIB.addReg(VAddr); in selectMUBUFAddr64Atomic()
4833 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFAddr64Atomic()
4835 MIB.addReg(SOffset); in selectMUBUFAddr64Atomic()
4837 MIB.addImm(0); in selectMUBUFAddr64Atomic()
4839 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFAddr64Atomic()
4840 MIB.addImm(Offset); in selectMUBUFAddr64Atomic()
4842 [=](MachineInstrBuilder &MIB) { in selectMUBUFAddr64Atomic()
4843 MIB.addImm(AMDGPU::CPol::GLC); // cpol in selectMUBUFAddr64Atomic()
4858 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFOffsetAtomic()
4859 MIB.addReg(RSrcReg); in selectMUBUFOffsetAtomic()
4861 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFOffsetAtomic()
4863 MIB.addReg(SOffset); in selectMUBUFOffsetAtomic()
4865 MIB.addImm(0); in selectMUBUFOffsetAtomic()
4867 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffsetAtomic()
4868 [=](MachineInstrBuilder &MIB) { MIB.addImm(AMDGPU::CPol::GLC); } // cpol in selectMUBUFOffsetAtomic()
4893 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm()
4909 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm32()
4912 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB, in renderTruncImm32() argument
4917 MIB.addImm(MI.getOperand(1).getCImm()->getSExtValue()); in renderTruncImm32()
4920 void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB, in renderNegateImm() argument
4925 MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue()); in renderNegateImm()
4928 void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB, in renderBitcastImm() argument
4935 MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); in renderBitcastImm()
4938 MIB.addImm(Op.getCImm()->getSExtValue()); in renderBitcastImm()
4942 void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB, in renderPopcntImm() argument
4947 MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation()); in renderPopcntImm()
4952 void AMDGPUInstructionSelector::renderTruncTImm(MachineInstrBuilder &MIB, in renderTruncTImm() argument
4955 MIB.addImm(MI.getOperand(OpIdx).getImm()); in renderTruncTImm()
4958 void AMDGPUInstructionSelector::renderExtractCPol(MachineInstrBuilder &MIB, in renderExtractCPol() argument
4962 MIB.addImm(MI.getOperand(OpIdx).getImm() & AMDGPU::CPol::ALL); in renderExtractCPol()
4965 void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB, in renderExtractSWZ() argument
4969 MIB.addImm((MI.getOperand(OpIdx).getImm() >> 3) & 1); in renderExtractSWZ()
4972 void AMDGPUInstructionSelector::renderSetGLC(MachineInstrBuilder &MIB, in renderSetGLC() argument
4976 MIB.addImm(MI.getOperand(OpIdx).getImm() | AMDGPU::CPol::GLC); in renderSetGLC()
4979 void AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB, in renderFrameIndex() argument
4982 MIB.addFrameIndex((MI.getOperand(1).getIndex())); in renderFrameIndex()