487   unsigned DstSize = DstTy.getSizeInBits();  in selectG_EXTRACT()  local
491   if (Offset % 32 != 0 || DstSize > 128)  in selectG_EXTRACT()
496   if (DstSize == 16)  in selectG_EXTRACT()
497     DstSize = 32;  in selectG_EXTRACT()
510                                                          DstSize / 32);  in selectG_EXTRACT()
537   const unsigned DstSize = DstTy.getSizeInBits();  in selectG_MERGE_VALUES()  local
539       TRI.getRegClassForSizeOnBank(DstSize, *DstBank);  in selectG_MERGE_VALUES()
575   const unsigned DstSize = DstTy.getSizeInBits();  in selectG_UNMERGE_VALUES()  local
588   ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);  in selectG_UNMERGE_VALUES()
736   unsigned DstSize = MRI->getType(DstReg).getSizeInBits();  in selectG_INSERT()  local
755       TRI.getRegClassForSizeOnBank(DstSize, *DstBank);  in selectG_INSERT()
762       TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank);  in selectG_INSERT()
1941   unsigned DstSize = DstTy.getSizeInBits();  in selectG_TRUNC()  local
1947       TRI.getRegClassForSizeOnBank(DstSize, *DstRB);  in selectG_TRUNC()
2017     int SubRegIdx = sizeToSubRegIndex(DstSize);  in selectG_TRUNC()
2073   const unsigned DstSize = DstTy.getSizeInBits();  in selectG_SZA_EXT()  local
2082     if (DstSize <= 32)  in selectG_SZA_EXT()
2089         TRI.getRegClassForSizeOnBank(DstSize, *DstBank);  in selectG_SZA_EXT()
2104   if (SrcBank->getID() == AMDGPU::VGPRRegBankID && DstSize <= 32) {  in selectG_SZA_EXT()
2128   if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) {  in selectG_SZA_EXT()
2129     const TargetRegisterClass &SrcRC = InReg && DstSize > 32 ?  in selectG_SZA_EXT()
2134     if (Signed && DstSize == 32 && (SrcSize == 8 || SrcSize == 16)) {  in selectG_SZA_EXT()
2147     if (DstSize > 32 && (SrcSize <= 32 || InReg)) {  in selectG_SZA_EXT()