Lines Matching refs:BaseOffset
1406 Register BaseOffset = MI.getOperand(HasVSrc ? 2 : 1).getReg(); in selectDSGWSIntrinsic() local
1407 const RegisterBank *OffsetRB = RBI.getRegBank(BaseOffset, *MRI, TRI); in selectDSGWSIntrinsic()
1411 MachineInstr *OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI); in selectDSGWSIntrinsic()
1426 BaseOffset = OffsetDef->getOperand(1).getReg(); in selectDSGWSIntrinsic()
1427 OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI); in selectDSGWSIntrinsic()
1440 std::tie(BaseOffset, ImmOffset) = in selectDSGWSIntrinsic()
1441 AMDGPU::getBaseWithConstantOffset(*MRI, BaseOffset); in selectDSGWSIntrinsic()
1446 if (!RBI.constrainGenericRegister(BaseOffset, AMDGPU::VGPR_32RegClass, *MRI)) in selectDSGWSIntrinsic()
1449 Readfirstlane->getOperand(1).setReg(BaseOffset); in selectDSGWSIntrinsic()
1450 BaseOffset = Readfirstlane->getOperand(0).getReg(); in selectDSGWSIntrinsic()
1452 if (!RBI.constrainGenericRegister(BaseOffset, in selectDSGWSIntrinsic()
1459 .addReg(BaseOffset) in selectDSGWSIntrinsic()