Lines Matching refs:SelectionDAG
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
64 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
66 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
68 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
70 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
71 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
74 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
109 SelectionDAG &DAG) const;
113 SelectionDAG &DAG) const;
114 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
115 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
120 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
126 SelectionDAG &DAG) const;
129 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
133 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
136 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
142 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
169 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
189 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
206 SelectionDAG &DAG) const override;
209 SelectionDAG &DAG,
220 SelectionDAG &DAG) const;
222 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
226 SelectionDAG &DAG) const override;
244 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { in isFsqrtCheap()
247 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
250 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
254 SelectionDAG &DAG) const = 0;
262 const SelectionDAG &DAG,
266 const SelectionDAG &DAG,
276 const SelectionDAG &DAG,
285 SDValue CreateLiveInRegister(SelectionDAG &DAG,
290 SDValue CreateLiveInRegister(SelectionDAG &DAG, in CreateLiveInRegister()
297 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, in CreateLiveInRegisterRaw()
305 SDValue loadStackInputValue(SelectionDAG &DAG,
310 SDValue storeStackInputValue(SelectionDAG &DAG,
316 SDValue loadInputValue(SelectionDAG &DAG,