Lines Matching refs:SDValue
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
64 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
66 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
68 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
70 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
71 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
74 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
81 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
84 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
87 unsigned Opc, SDValue LHS,
89 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
92 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
93 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
94 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
95 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
96 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
97 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
98 SDValue RHS, DAGCombinerInfo &DCI) const;
99 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
101 bool isConstantCostlierToNegate(SDValue N) const;
102 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
103 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
104 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
108 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
112 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
114 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
115 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
124 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
129 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
133 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
136 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
142 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
143 SmallVectorImpl<SDValue> &Results) const;
152 bool mayIgnoreSignedZero(SDValue Op) const;
154 static inline SDValue stripBitcast(SDValue Val) { in stripBitcast()
167 bool isZExtFree(SDValue Val, EVT VT2) const override;
169 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
203 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
205 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
208 SDValue addTokenForArgument(SDValue Chain,
213 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
214 SmallVectorImpl<SDValue> &InVals,
216 SDValue LowerCall(CallLoweringInfo &CLI,
217 SmallVectorImpl<SDValue> &InVals) const override;
219 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
222 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
223 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
225 SmallVectorImpl<SDValue> &Results,
228 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
229 SDValue RHS, SDValue True, SDValue False,
230 SDValue CC, DAGCombinerInfo &DCI) const;
244 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { in isFsqrtCheap()
247 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
250 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
259 void computeKnownBitsForTargetNode(const SDValue Op,
265 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
275 bool isKnownNeverNaNForTargetNode(SDValue Op,
285 SDValue CreateLiveInRegister(SelectionDAG &DAG,
290 SDValue CreateLiveInRegister(SelectionDAG &DAG, in CreateLiveInRegister()
297 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, in CreateLiveInRegisterRaw()
305 SDValue loadStackInputValue(SelectionDAG &DAG,
310 SDValue storeStackInputValue(SelectionDAG &DAG,
312 SDValue Chain,
313 SDValue ArgVal,
316 SDValue loadInputValue(SelectionDAG &DAG,