Lines Matching refs:SL
1251 SDLoc SL(Op); in LowerCONCAT_VECTORS() local
1252 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0)); in LowerCONCAT_VECTORS()
1253 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1)); in LowerCONCAT_VECTORS()
1255 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi }); in LowerCONCAT_VECTORS()
1256 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1371 SDLoc SL(Op); in split64BitValue() local
1373 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1375 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in split64BitValue()
1376 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in split64BitValue()
1378 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1379 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1385 SDLoc SL(Op); in getLoHalf64() local
1387 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1388 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in getLoHalf64()
1389 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1393 SDLoc SL(Op); in getHiHalf64() local
1395 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1396 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in getHiHalf64()
1397 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1438 SDLoc SL(Op); in SplitVectorLoad() local
1446 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1460 std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG); in SplitVectorLoad()
1466 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT, in SplitVectorLoad()
1469 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Size)); in SplitVectorLoad()
1471 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(), in SplitVectorLoad()
1478 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
1480 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1481 DAG.getVectorIdxConstant(0, SL)); in SplitVectorLoad()
1483 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
1485 DAG.getVectorIdxConstant(LoVT.getVectorNumElements(), SL)); in SplitVectorLoad()
1488 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1491 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1500 SDLoc SL(Op); in WidenOrSplitVectorLoad() local
1519 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue, in WidenOrSplitVectorLoad()
1522 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
1523 DAG.getVectorIdxConstant(0, SL)), in WidenOrSplitVectorLoad()
1525 SL); in WidenOrSplitVectorLoad()
1542 SDLoc SL(Op); in SplitVectorStore() local
1550 std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG); in SplitVectorStore()
1552 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize()); in SplitVectorStore()
1560 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign, in SplitVectorStore()
1563 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size), in SplitVectorStore()
1566 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
2016 SDLoc SL(Op); in LowerFREM() local
2022 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
2023 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2024 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2026 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags); in LowerFREM()
2030 SDLoc SL(Op); in LowerFCEIL() local
2037 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2039 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFCEIL()
2040 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFCEIL()
2045 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
2046 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
2047 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
2049 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
2051 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2054 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL, in extractF64Exponent() argument
2059 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in extractF64Exponent()
2061 DAG.getConstant(FractBits - 32, SL, MVT::i32), in extractF64Exponent()
2062 DAG.getConstant(ExpBits, SL, MVT::i32)); in extractF64Exponent()
2063 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2064 DAG.getConstant(1023, SL, MVT::i32)); in extractF64Exponent()
2070 SDLoc SL(Op); in LowerFTRUNC() local
2075 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerFTRUNC()
2081 SDValue Exp = extractF64Exponent(Hi, SL, DAG); in LowerFTRUNC()
2086 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32); in LowerFTRUNC()
2087 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2090 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2091 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2093 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2095 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64); in LowerFTRUNC()
2097 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2098 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
2099 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2104 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32); in LowerFTRUNC()
2106 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2107 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFTRUNC()
2109 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2110 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2112 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2116 SDLoc SL(Op); in LowerFRINT() local
2122 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64); in LowerFRINT()
2123 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2127 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2128 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2130 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2133 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64); in LowerFRINT()
2137 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
2139 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFRINT()
2155 SDLoc SL(Op); in LowerFROUND() local
2159 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2163 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2165 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2167 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFROUND()
2168 const SDValue One = DAG.getConstantFP(1.0, SL, VT); in LowerFROUND()
2169 const SDValue Half = DAG.getConstantFP(0.5, SL, VT); in LowerFROUND()
2171 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X); in LowerFROUND()
2176 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
2178 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero); in LowerFROUND()
2180 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND()
2184 SDLoc SL(Op); in LowerFFLOOR() local
2191 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2193 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFFLOOR()
2194 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64); in LowerFFLOOR()
2199 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2200 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
2201 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2203 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2205 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2212 SDLoc SL(Op); in LowerFLOG() local
2214 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand); in LowerFLOG()
2215 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOG()
2217 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand); in LowerFLOG()
2223 SDLoc SL(Op); in lowerFEXP() local
2226 const SDValue K = DAG.getConstantFP(numbers::log2e, SL, VT); in lowerFEXP()
2227 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags()); in lowerFEXP()
2228 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags()); in lowerFEXP()
2240 SDLoc SL(Op); in LowerCTLZ_CTTZ() local
2255 SDValue NewOpr = DAG.getNode(NewOpc, SL, MVT::i32, Src); in LowerCTLZ_CTTZ()
2257 const SDValue Const32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ()
2258 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const32); in LowerCTLZ_CTTZ()
2266 SDValue OprLo = DAG.getNode(NewOpc, SL, MVT::i32, Lo); in LowerCTLZ_CTTZ()
2267 SDValue OprHi = DAG.getNode(NewOpc, SL, MVT::i32, Hi); in LowerCTLZ_CTTZ()
2275 const SDValue Const32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ()
2277 OprLo = DAG.getNode(AddOpc, SL, MVT::i32, OprLo, Const32); in LowerCTLZ_CTTZ()
2279 OprHi = DAG.getNode(AddOpc, SL, MVT::i32, OprHi, Const32); in LowerCTLZ_CTTZ()
2282 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ()
2284 const SDValue Const64 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ()
2285 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ()
2288 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
2319 SDLoc SL(Op); in LowerINT_TO_FP32() local
2349 ISD::SRA, SL, MVT::i32, DAG.getNode(ISD::XOR, SL, MVT::i32, Lo, Hi), in LowerINT_TO_FP32()
2350 DAG.getConstant(31, SL, MVT::i32)); in LowerINT_TO_FP32()
2352 DAG.getNode(ISD::ADD, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
2355 ShAmt = DAG.getNode(AMDGPUISD::FFBH_I32, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
2358 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
2359 DAG.getConstant(1, SL, MVT::i32)); in LowerINT_TO_FP32()
2360 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32()
2365 Sign = DAG.getNode(ISD::SRA, SL, MVT::i64, Src, in LowerINT_TO_FP32()
2366 DAG.getConstant(63, SL, MVT::i64)); in LowerINT_TO_FP32()
2368 DAG.getNode(ISD::XOR, SL, MVT::i64, in LowerINT_TO_FP32()
2369 DAG.getNode(ISD::ADD, SL, MVT::i64, Src, Sign), Sign); in LowerINT_TO_FP32()
2373 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
2377 SDValue Norm = DAG.getNode(ISD::SHL, SL, MVT::i64, Src, ShAmt); in LowerINT_TO_FP32()
2382 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
2383 DAG.getConstant(1, SL, MVT::i32), Lo); in LowerINT_TO_FP32()
2385 Norm = DAG.getNode(ISD::OR, SL, MVT::i32, Hi, Adjust); in LowerINT_TO_FP32()
2389 SDValue FVal = DAG.getNode(Opc, SL, MVT::f32, Norm); in LowerINT_TO_FP32()
2393 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
2397 return DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f32, FVal, ShAmt); in LowerINT_TO_FP32()
2402 SDValue Exp = DAG.getNode(ISD::SHL, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
2403 DAG.getConstant(23, SL, MVT::i32)); in LowerINT_TO_FP32()
2405 DAG.getNode(ISD::ADD, SL, MVT::i32, in LowerINT_TO_FP32()
2406 DAG.getNode(ISD::BITCAST, SL, MVT::i32, FVal), Exp); in LowerINT_TO_FP32()
2409 Sign = DAG.getNode(ISD::SHL, SL, MVT::i32, in LowerINT_TO_FP32()
2410 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Sign), in LowerINT_TO_FP32()
2411 DAG.getConstant(31, SL, MVT::i32)); in LowerINT_TO_FP32()
2412 IVal = DAG.getNode(ISD::OR, SL, MVT::i32, IVal, Sign); in LowerINT_TO_FP32()
2414 return DAG.getNode(ISD::BITCAST, SL, MVT::f32, IVal); in LowerINT_TO_FP32()
2419 SDLoc SL(Op); in LowerINT_TO_FP64() local
2426 SL, MVT::f64, Hi); in LowerINT_TO_FP64()
2428 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2430 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
2431 DAG.getConstant(32, SL, MVT::i32)); in LowerINT_TO_FP64()
2433 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
2515 SDLoc SL(Op); in LowerFP_TO_INT64() local
2531 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src); in LowerFP_TO_INT64()
2539 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
2540 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc), in LowerFP_TO_INT64()
2541 DAG.getConstant(31, SL, MVT::i32)); in LowerFP_TO_INT64()
2542 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
2548 SL, SrcVT); in LowerFP_TO_INT64()
2550 SL, SrcVT); in LowerFP_TO_INT64()
2552 K0 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*2^-32*/ 0x2f800000)), SL, in LowerFP_TO_INT64()
2554 K1 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*-2^32*/ 0xcf800000)), SL, in LowerFP_TO_INT64()
2558 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); in LowerFP_TO_INT64()
2560 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
2562 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc); in LowerFP_TO_INT64()
2566 SL, MVT::i32, FloorMul); in LowerFP_TO_INT64()
2567 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
2569 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
2570 DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi})); in LowerFP_TO_INT64()
2575 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
2576 DAG.getBuildVector(MVT::v2i32, SL, {Sign, Sign})); in LowerFP_TO_INT64()
2579 DAG.getNode(ISD::SUB, SL, MVT::i64, in LowerFP_TO_INT64()
2580 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign); in LowerFP_TO_INT64()
2862 SDLoc SL(N); in performLoadCombine() local
2896 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
2899 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
2918 SDLoc SL(N); in performStoreCombine() local
2950 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
2952 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
2956 return DAG.getStore(SN->getChain(), SL, CastVal, in performStoreCombine()
2973 SDLoc SL(N); in performAssertSZExtCombine() local
2978 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
2979 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); in performAssertSZExtCombine()
3013 DAGCombinerInfo &DCI, const SDLoc &SL, in splitBinaryBitConstantOpImpl() argument
3020 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3021 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3023 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS); in splitBinaryBitConstantOpImpl()
3024 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS); in splitBinaryBitConstantOpImpl()
3031 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd}); in splitBinaryBitConstantOpImpl()
3032 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
3048 SDLoc SL(N); in performShlCombine() local
3063 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL, in performShlCombine()
3064 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) }); in performShlCombine()
3065 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
3076 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
3077 return DAG.getZExtOrTrunc(Shl, SL, VT); in performShlCombine()
3092 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32); in performShlCombine()
3094 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3095 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
3097 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performShlCombine()
3099 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
3100 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
3113 SDLoc SL(N); in performSraCombine() local
3119 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3120 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3122 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
3123 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3130 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3131 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
3132 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3148 SDLoc SL(N); in performSrlCombine() local
3158 ISD::AND, SL, VT, in performSrlCombine()
3159 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
3160 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
3174 SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performSrlCombine()
3178 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32); in performSrlCombine()
3179 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
3181 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
3183 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
3188 SDLoc SL(N); in performTruncateCombine() local
3201 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3205 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
3222 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3226 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
3252 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
3257 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT); in performTruncateCombine()
3261 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
3263 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
3275 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL, in getMul24() argument
3279 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3285 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
3286 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
3288 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi); in getMul24()
3488 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, in performCtlz_CttzCombine() argument
3506 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
3517 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
3525 const SDLoc &SL, in distributeOpThroughSelect() argument
3532 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
3535 return DAG.getNode(Op, SL, VT, NewSelect); in distributeOpThroughSelect()
3568 SDLoc SL(N); in foldFreeOpFromSelect() local
3587 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
3594 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
3597 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect); in foldFreeOpFromSelect()
3630 SDLoc SL(N); in performSelectCombine() local
3634 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC); in performSelectCombine()
3635 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
3717 SDLoc SL(N); in performFNegCombine() local
3728 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
3733 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3737 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3741 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3756 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3758 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3762 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3781 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
3784 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3788 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); in performFNegCombine()
3792 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3814 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
3815 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3818 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
3822 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3828 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
3830 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
3835 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res); in performFNegCombine()
3858 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
3866 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
3867 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
3874 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3882 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
3883 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
3889 SDLoc SL(N); in performFNegCombine() local
3895 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
3896 DAG.getConstant(0x8000, SL, SrcVT)); in performFNegCombine()
3897 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
3915 SDLoc SL(N); in performFAbsCombine() local
3920 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
3921 DAG.getConstant(0x7fff, SL, SrcVT)); in performFAbsCombine()
3922 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
3967 SDLoc SL(N); in PerformDAGCombine() local
3973 return DAG.getBuildVector(DestVT, SL, CastedElts); in PerformDAGCombine()
3987 SDLoc SL(N); in PerformDAGCombine() local
3989 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
3990 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
3991 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
3992 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
3997 SDLoc SL(N); in PerformDAGCombine() local
3999 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
4000 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
4001 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
4003 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()
4155 const SDLoc &SL, in CreateLiveInRegister() argument
4171 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT); in CreateLiveInRegister()
4190 const SDLoc &SL, in loadStackInputValue() argument
4199 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, Align(4), in loadStackInputValue()
4205 const SDLoc &SL, in storeStackInputValue() argument
4213 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32); in storeStackInputValue()
4216 DAG.getCopyFromReg(Chain, SL, Info->getStackPtrOffsetReg(), MVT::i32); in storeStackInputValue()
4217 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr); in storeStackInputValue()
4218 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, Align(4), in storeStackInputValue()
4225 EVT VT, const SDLoc &SL, in loadInputValue() argument
4230 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) : in loadInputValue()
4231 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset()); in loadInputValue()
4238 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()
4239 DAG.getShiftAmountConstant(Shift, VT, SL)); in loadInputValue()
4240 return DAG.getNode(ISD::AND, SL, VT, V, in loadInputValue()
4241 DAG.getConstant(Mask >> Shift, SL, VT)); in loadInputValue()