Lines Matching refs:N0
2588 SDValue N0 = Op.getOperand(0); in LowerFP_TO_FP16() local
2591 if (N0.getValueType() == MVT::f32) in LowerFP_TO_FP16()
2592 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
2599 assert(N0.getSimpleValueType() == MVT::f64); in LowerFP_TO_FP16()
2607 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0); in LowerFP_TO_FP16()
2966 SDValue N0 = N->getOperand(0); in performAssertSZExtCombine() local
2970 if (N0.getOpcode() == ISD::TRUNCATE) { in performAssertSZExtCombine()
2975 SDValue Src = N0.getOperand(0); in performAssertSZExtCombine()
3276 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24() argument
3279 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3285 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
3286 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
3313 SDValue N0 = N->getOperand(0); in performMulCombine() local
3320 if (N0.getOpcode() == ISD::ANY_EXTEND) in performMulCombine()
3321 N0 = N0.getOperand(0); in performMulCombine()
3328 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) { in performMulCombine()
3329 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
3331 Mul = getMul24(DAG, DL, N0, N1, Size, false); in performMulCombine()
3332 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine()
3333 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
3335 Mul = getMul24(DAG, DL, N0, N1, Size, true); in performMulCombine()
3354 SDValue N0 = N->getOperand(0); in performMulLoHiCombine() local
3361 if (N0.getOpcode() == ISD::ANY_EXTEND) in performMulLoHiCombine()
3362 N0 = N0.getOperand(0); in performMulLoHiCombine()
3369 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) { in performMulLoHiCombine()
3370 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulLoHiCombine()
3374 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulLoHiCombine()
3375 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulLoHiCombine()
3383 SDValue Lo = DAG.getNode(LoOpcode, DL, MVT::i32, N0, N1); in performMulLoHiCombine()
3384 SDValue Hi = DAG.getNode(HiOpcode, DL, MVT::i32, N0, N1); in performMulLoHiCombine()
3408 SDValue N0 = N->getOperand(0); in performMulhsCombine() local
3411 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
3414 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulhsCombine()
3417 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1); in performMulhsCombine()
3441 SDValue N0 = N->getOperand(0); in performMulhuCombine() local
3444 if (!isU24(N0, DAG) || !isU24(N1, DAG)) in performMulhuCombine()
3447 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulhuCombine()
3450 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1); in performMulhuCombine()
3697 SDValue N0 = N->getOperand(0); in performFNegCombine() local
3700 unsigned Opc = N0.getOpcode(); in performFNegCombine()
3706 if (N0.hasOneUse()) { in performFNegCombine()
3713 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode()))) in performFNegCombine()
3720 if (!mayIgnoreSignedZero(N0)) in performFNegCombine()
3724 SDValue LHS = N0.getOperand(0); in performFNegCombine()
3725 SDValue RHS = N0.getOperand(1); in performFNegCombine()
3737 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3740 if (!N0.hasOneUse()) in performFNegCombine()
3741 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3748 SDValue LHS = N0.getOperand(0); in performFNegCombine()
3749 SDValue RHS = N0.getOperand(1); in performFNegCombine()
3758 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3761 if (!N0.hasOneUse()) in performFNegCombine()
3762 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3768 if (!mayIgnoreSignedZero(N0)) in performFNegCombine()
3772 SDValue LHS = N0.getOperand(0); in performFNegCombine()
3773 SDValue MHS = N0.getOperand(1); in performFNegCombine()
3774 SDValue RHS = N0.getOperand(2); in performFNegCombine()
3791 if (!N0.hasOneUse()) in performFNegCombine()
3792 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3806 SDValue LHS = N0.getOperand(0); in performFNegCombine()
3807 SDValue RHS = N0.getOperand(1); in performFNegCombine()
3818 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
3821 if (!N0.hasOneUse()) in performFNegCombine()
3822 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3828 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
3830 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
3834 if (!N0.hasOneUse()) { in performFNegCombine()
3836 DAG.ReplaceAllUsesWith(N0, Neg); in performFNegCombine()
3854 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine()
3861 if (!N0.hasOneUse()) in performFNegCombine()
3867 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
3870 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine()
3875 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine()
3878 if (!N0.hasOneUse()) in performFNegCombine()
3883 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
3891 SDValue Src = N0.getOperand(0); in performFNegCombine()
3907 SDValue N0 = N->getOperand(0); in performFAbsCombine() local
3909 if (!N0.hasOneUse()) in performFAbsCombine()
3912 switch (N0.getOpcode()) { in performFAbsCombine()
3916 SDValue Src = N0.getOperand(0); in performFAbsCombine()