Lines Matching refs:ShuffleVectorPseudo
54 struct ShuffleVectorPseudo { struct
58 ShuffleVectorPseudo(unsigned Opc, Register Dst, in ShuffleVectorPseudo() function
61 ShuffleVectorPseudo() = default;
219 ShuffleVectorPseudo &MatchInfo) { in matchREV()
235 MatchInfo = ShuffleVectorPseudo(AArch64::G_REV64, Dst, {Src}); in matchREV()
248 ShuffleVectorPseudo &MatchInfo) { in matchTRN()
259 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchTRN()
269 ShuffleVectorPseudo &MatchInfo) { in matchUZP()
280 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchUZP()
285 ShuffleVectorPseudo &MatchInfo) { in matchZip()
296 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchZip()
303 ShuffleVectorPseudo &MatchInfo) { in matchDupFromInsertVectorElt()
334 MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), in matchDupFromInsertVectorElt()
342 ShuffleVectorPseudo &MatchInfo) { in matchDupFromBuildVector()
352 ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), {Reg}); in matchDupFromBuildVector()
357 ShuffleVectorPseudo &MatchInfo) { in matchDup()
374 ShuffleVectorPseudo &MatchInfo) { in matchEXT()
390 MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V2, Imm}); in matchEXT()
397 ShuffleVectorPseudo &MatchInfo) { in applyShuffleVectorPseudo()
407 static bool applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) { in applyEXT()