Lines Matching refs:TargetOpcode
651 MIB.buildInstr(TargetOpcode::REG_SEQUENCE, {DesiredClass}, {}); in createTuple()
756 case TargetOpcode::G_SHL: in selectBinaryOp()
758 case TargetOpcode::G_LSHR: in selectBinaryOp()
760 case TargetOpcode::G_ASHR: in selectBinaryOp()
767 case TargetOpcode::G_PTR_ADD: in selectBinaryOp()
769 case TargetOpcode::G_SHL: in selectBinaryOp()
771 case TargetOpcode::G_LSHR: in selectBinaryOp()
773 case TargetOpcode::G_ASHR: in selectBinaryOp()
784 case TargetOpcode::G_FADD: in selectBinaryOp()
786 case TargetOpcode::G_FSUB: in selectBinaryOp()
788 case TargetOpcode::G_FMUL: in selectBinaryOp()
790 case TargetOpcode::G_FDIV: in selectBinaryOp()
797 case TargetOpcode::G_FADD: in selectBinaryOp()
799 case TargetOpcode::G_FSUB: in selectBinaryOp()
801 case TargetOpcode::G_FMUL: in selectBinaryOp()
803 case TargetOpcode::G_FDIV: in selectBinaryOp()
805 case TargetOpcode::G_OR: in selectBinaryOp()
823 const bool isStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreUIOp()
868 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg); in copySubReg()
991 if (I.getOpcode() == TargetOpcode::G_ZEXT) { in selectCopy()
1013 case TargetOpcode::G_SITOFP: in selectFPConvOpc()
1015 case TargetOpcode::G_UITOFP: in selectFPConvOpc()
1017 case TargetOpcode::G_FPTOSI: in selectFPConvOpc()
1019 case TargetOpcode::G_FPTOUI: in selectFPConvOpc()
1026 case TargetOpcode::G_SITOFP: in selectFPConvOpc()
1028 case TargetOpcode::G_UITOFP: in selectFPConvOpc()
1030 case TargetOpcode::G_FPTOSI: in selectFPConvOpc()
1032 case TargetOpcode::G_FPTOUI: in selectFPConvOpc()
1044 case TargetOpcode::G_SITOFP: in selectFPConvOpc()
1046 case TargetOpcode::G_UITOFP: in selectFPConvOpc()
1048 case TargetOpcode::G_FPTOSI: in selectFPConvOpc()
1050 case TargetOpcode::G_FPTOUI: in selectFPConvOpc()
1057 case TargetOpcode::G_SITOFP: in selectFPConvOpc()
1059 case TargetOpcode::G_UITOFP: in selectFPConvOpc()
1061 case TargetOpcode::G_FPTOSI: in selectFPConvOpc()
1063 case TargetOpcode::G_FPTOUI: in selectFPConvOpc()
1375 if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT || in getTestBitReg()
1376 Opc == TargetOpcode::G_TRUNC) { in getTestBitReg()
1377 if (Opc == TargetOpcode::G_ZEXT) in getTestBitReg()
1396 case TargetOpcode::G_AND: in getTestBitReg()
1397 case TargetOpcode::G_XOR: { in getTestBitReg()
1416 case TargetOpcode::G_ASHR: in getTestBitReg()
1417 case TargetOpcode::G_LSHR: in getTestBitReg()
1418 case TargetOpcode::G_SHL: { in getTestBitReg()
1439 case TargetOpcode::G_AND: in getTestBitReg()
1444 case TargetOpcode::G_SHL: in getTestBitReg()
1452 case TargetOpcode::G_ASHR: in getTestBitReg()
1460 case TargetOpcode::G_LSHR: in getTestBitReg()
1467 case TargetOpcode::G_XOR: in getTestBitReg()
1527 assert(AndInst.getOpcode() == TargetOpcode::G_AND && "Expected G_AND only?"); in tryOptAndIntoCompareBranch()
1588 assert(FCmp.getOpcode() == TargetOpcode::G_FCMP); in selectCompareBranchFedByFCmp()
1589 assert(I.getOpcode() == TargetOpcode::G_BRCOND); in selectCompareBranchFedByFCmp()
1607 assert(ICmp.getOpcode() == TargetOpcode::G_ICMP); in tryOptCompareBranchFedByICmp()
1608 assert(I.getOpcode() == TargetOpcode::G_BRCOND); in tryOptCompareBranchFedByICmp()
1626 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1661 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1693 assert(ICmp.getOpcode() == TargetOpcode::G_ICMP); in selectCompareBranchFedByICmp()
1694 assert(I.getOpcode() == TargetOpcode::G_BRCOND); in selectCompareBranchFedByICmp()
1716 if (CCMIOpc == TargetOpcode::G_FCMP) in selectCompareBranch()
1718 if (CCMIOpc == TargetOpcode::G_ICMP) in selectCompareBranch()
1787 assert(I.getOpcode() == TargetOpcode::G_SHL); in selectVectorSHL()
1832 assert(I.getOpcode() == TargetOpcode::G_ASHR || in selectVectorAshrLshr()
1833 I.getOpcode() == TargetOpcode::G_LSHR); in selectVectorAshrLshr()
1842 bool IsASHR = I.getOpcode() == TargetOpcode::G_ASHR; in selectVectorAshrLshr()
1964 case TargetOpcode::G_STORE: { in preISelLower()
1979 case TargetOpcode::G_PTR_ADD: in preISelLower()
1981 case TargetOpcode::G_LOAD: { in preISelLower()
2005 case TargetOpcode::G_UITOFP: in preISelLower()
2006 case TargetOpcode::G_SITOFP: { in preISelLower()
2018 if (I.getOpcode() == TargetOpcode::G_SITOFP) in preISelLower()
2041 assert(I.getOpcode() == TargetOpcode::G_PTR_ADD && "Expected G_PTR_ADD"); in convertPtrAddToAdd()
2059 I.setDesc(TII.get(TargetOpcode::G_ADD)); in convertPtrAddToAdd()
2073 I.setDesc(TII.get(TargetOpcode::G_SUB)); in convertPtrAddToAdd()
2082 assert(I.getOpcode() == TargetOpcode::G_SHL && "unexpected op"); in earlySelectSHL()
2113 assert(I.getOpcode() == TargetOpcode::G_STORE && "Expected G_STORE"); in contractCrossBankCopyIntoStore()
2180 case TargetOpcode::G_SEXT: in earlySelect()
2186 case TargetOpcode::G_BR: in earlySelect()
2188 case TargetOpcode::G_SHL: in earlySelect()
2190 case TargetOpcode::G_CONSTANT: { in earlySelect()
2211 I.setDesc(TII.get(TargetOpcode::COPY)); in earlySelect()
2215 case TargetOpcode::G_ADD: { in earlySelect()
2242 return getOpcodeDef(TargetOpcode::G_ICMP, Reg, MRI); in earlySelect()
2249 auto *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, ZExt, MRI); in earlySelect()
2276 case TargetOpcode::G_OR: { in earlySelect()
2310 case TargetOpcode::G_FENCE: { in earlySelect()
2344 if (!I.isPreISelOpcode() || Opcode == TargetOpcode::G_PHI) { in select()
2347 if (Opcode == TargetOpcode::LOAD_STACK_GUARD) in select()
2350 if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) { in select()
2372 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
2412 case TargetOpcode::G_SBFX: in select()
2413 case TargetOpcode::G_UBFX: { in select()
2417 bool IsSigned = Opcode == TargetOpcode::G_SBFX; in select()
2435 case TargetOpcode::G_BRCOND: in select()
2438 case TargetOpcode::G_BRINDIRECT: { in select()
2443 case TargetOpcode::G_BRJT: in select()
2470 case TargetOpcode::G_BSWAP: { in select()
2507 case TargetOpcode::G_FCONSTANT: in select()
2508 case TargetOpcode::G_CONSTANT: { in select()
2509 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT; in select()
2621 case TargetOpcode::G_EXTRACT: { in select()
2647 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}) in select()
2676 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in select()
2685 case TargetOpcode::G_INSERT: { in select()
2719 case TargetOpcode::G_FRAME_INDEX: { in select()
2735 case TargetOpcode::G_GLOBAL_VALUE: { in select()
2762 case TargetOpcode::G_ZEXTLOAD: in select()
2763 case TargetOpcode::G_LOAD: in select()
2764 case TargetOpcode::G_STORE: { in select()
2766 bool IsZExtLoad = I.getOpcode() == TargetOpcode::G_ZEXTLOAD; in select()
2804 MIB.buildInstr(TargetOpcode::COPY, {NewVal}, {}) in select()
2838 auto Copy = MIB.buildInstr(TargetOpcode::COPY, {MemTy}, {}) in select()
2903 if (Opcode == TargetOpcode::G_STORE) { in select()
2943 case TargetOpcode::G_SMULH: in select()
2944 case TargetOpcode::G_UMULH: { in select()
2963 unsigned NewOpc = I.getOpcode() == TargetOpcode::G_SMULH ? AArch64::SMULHrr in select()
2971 case TargetOpcode::G_LSHR: in select()
2972 case TargetOpcode::G_ASHR: in select()
2976 case TargetOpcode::G_SHL: in select()
2977 if (Opcode == TargetOpcode::G_SHL && in select()
2994 auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {}) in select()
3001 case TargetOpcode::G_OR: { in select()
3023 case TargetOpcode::G_PTR_ADD: { in select()
3028 case TargetOpcode::G_SADDO: in select()
3029 case TargetOpcode::G_UADDO: in select()
3030 case TargetOpcode::G_SSUBO: in select()
3031 case TargetOpcode::G_USUBO: { in select()
3047 case TargetOpcode::G_PTRMASK: { in select()
3061 case TargetOpcode::G_PTRTOINT: in select()
3062 case TargetOpcode::G_TRUNC: { in select()
3095 } else if (Opcode == TargetOpcode::G_TRUNC && DstTy == LLT::scalar(32) && in select()
3108 I.setDesc(TII.get(TargetOpcode::COPY)); in select()
3128 if (Opcode == TargetOpcode::G_PTRTOINT) { in select()
3130 I.setDesc(TII.get(TargetOpcode::COPY)); in select()
3138 case TargetOpcode::G_ANYEXT: { in select()
3185 case TargetOpcode::G_ZEXT: in select()
3186 case TargetOpcode::G_SEXT_INREG: in select()
3187 case TargetOpcode::G_SEXT: { in select()
3192 const bool IsSigned = Opcode != TargetOpcode::G_ZEXT; in select()
3202 if (Opcode == TargetOpcode::G_SEXT_INREG) in select()
3221 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in select()
3275 if (Opcode != TargetOpcode::G_SEXT_INREG) { in select()
3309 case TargetOpcode::G_SITOFP: in select()
3310 case TargetOpcode::G_UITOFP: in select()
3311 case TargetOpcode::G_FPTOSI: in select()
3312 case TargetOpcode::G_FPTOUI: { in select()
3326 case TargetOpcode::G_FREEZE: in select()
3329 case TargetOpcode::G_INTTOPTR: in select()
3334 case TargetOpcode::G_BITCAST: in select()
3342 case TargetOpcode::G_SELECT: { in select()
3362 case TargetOpcode::G_ICMP: { in select()
3382 case TargetOpcode::G_FCMP: { in select()
3392 case TargetOpcode::G_VASTART: in select()
3395 case TargetOpcode::G_INTRINSIC: in select()
3397 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: in select()
3399 case TargetOpcode::G_IMPLICIT_DEF: { in select()
3400 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); in select()
3408 case TargetOpcode::G_BLOCK_ADDR: { in select()
3448 case TargetOpcode::G_INTRINSIC_TRUNC: in select()
3450 case TargetOpcode::G_INTRINSIC_ROUND: in select()
3452 case TargetOpcode::G_BUILD_VECTOR: in select()
3454 case TargetOpcode::G_MERGE_VALUES: in select()
3456 case TargetOpcode::G_UNMERGE_VALUES: in select()
3458 case TargetOpcode::G_SHUFFLE_VECTOR: in select()
3460 case TargetOpcode::G_EXTRACT_VECTOR_ELT: in select()
3462 case TargetOpcode::G_INSERT_VECTOR_ELT: in select()
3464 case TargetOpcode::G_CONCAT_VECTORS: in select()
3466 case TargetOpcode::G_JUMP_TABLE: in select()
3468 case TargetOpcode::G_VECREDUCE_FADD: in select()
3469 case TargetOpcode::G_VECREDUCE_ADD: in select()
3471 case TargetOpcode::G_MEMCPY: in select()
3472 case TargetOpcode::G_MEMCPY_INLINE: in select()
3473 case TargetOpcode::G_MEMMOVE: in select()
3474 case TargetOpcode::G_MEMSET: in select()
3486 if (I.getOpcode() == TargetOpcode::G_VECREDUCE_ADD) { in selectReduction()
3493 auto Copy = MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}) in selectReduction()
3518 if (I.getOpcode() == TargetOpcode::G_VECREDUCE_FADD) { in selectReduction()
3538 case TargetOpcode::G_MEMCPY: in selectMOPS()
3539 case TargetOpcode::G_MEMCPY_INLINE: in selectMOPS()
3542 case TargetOpcode::G_MEMMOVE: in selectMOPS()
3545 case TargetOpcode::G_MEMSET: in selectMOPS()
3594 assert(I.getOpcode() == TargetOpcode::G_BRJT && "Expected G_BRJT"); in selectBrJT()
3614 assert(I.getOpcode() == TargetOpcode::G_JUMP_TABLE && "Expected jump table"); in selectJumpTable()
3948 auto Undef = MIRBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstRC}, {}); in emitScalarToVector()
3953 .buildInstr(TargetOpcode::INSERT_SUBREG, {DstRC}, {Undef, Scalar}) in emitScalarToVector()
3974 assert(I.getOpcode() == TargetOpcode::G_MERGE_VALUES && "unexpected opcode"); in selectMergeValues()
3990 auto Tmp = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstTy}, {}); in selectMergeValues()
4014 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectMergeValues()
4022 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectMergeValues()
4104 auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {*DstReg}, {}) in emitExtractVectorElt()
4132 assert(I.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT && in selectExtractElt()
4199 assert(I.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in selectUnmergeValues()
4261 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF), in selectUnmergeValues()
4268 TII.get(TargetOpcode::INSERT_SUBREG), InsertReg) in selectUnmergeValues()
4286 auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {}) in selectUnmergeValues()
4319 assert(I.getOpcode() == TargetOpcode::G_CONCAT_VECTORS && in selectConcatVectors()
4737 case TargetOpcode::G_SADDO: in emitOverflowOp()
4739 case TargetOpcode::G_UADDO: in emitOverflowOp()
4741 case TargetOpcode::G_SSUBO: in emitOverflowOp()
4743 case TargetOpcode::G_USUBO: in emitOverflowOp()
4777 if (Opcode == TargetOpcode::G_AND || Opcode == TargetOpcode::G_OR) { in canEmitConjunction()
4778 bool IsOR = Opcode == TargetOpcode::G_OR; in canEmitConjunction()
4805 assert(Opcode == TargetOpcode::G_AND && "Must be G_AND"); in canEmitConjunction()
4895 bool IsOR = Opcode == TargetOpcode::G_OR; in emitConjunctionRec()
4923 if (Opcode == TargetOpcode::G_OR) { in emitConjunctionRec()
4940 assert(Opcode == TargetOpcode::G_AND && in emitConjunctionRec()
5014 if (UI.getOpcode() != TargetOpcode::G_SELECT) in tryOptSelect()
5021 if (CondOpc != TargetOpcode::G_ICMP && CondOpc != TargetOpcode::G_FCMP) { in tryOptSelect()
5028 if (CondOpc == TargetOpcode::G_ICMP) { in tryOptSelect()
5114 LHSDef->getOpcode() == TargetOpcode::G_AND) { in tryFoldIntegerCompare()
5188 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in selectShuffleVector()
5239 if (MI.getOpcode() != TargetOpcode::G_SEXT && in selectUSMovFromExtend()
5240 MI.getOpcode() != TargetOpcode::G_ZEXT && in selectUSMovFromExtend()
5241 MI.getOpcode() != TargetOpcode::G_ANYEXT) in selectUSMovFromExtend()
5243 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SEXT; in selectUSMovFromExtend()
5251 MachineInstr *Extract = getOpcodeDef(TargetOpcode::G_EXTRACT_VECTOR_ELT, in selectUSMovFromExtend()
5304 assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT); in selectInsertElt()
5364 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}) in selectInsertElt()
5396 auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {Dst}, {}) in emitConstantVector()
5417 assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR); in tryOptConstantBuildVec()
5428 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI); in tryOptConstantBuildVec()
5432 else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT, in tryOptConstantBuildVec()
5463 return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), in tryOptBuildVecToSubregToReg()
5488 assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR); in selectBuildVector()
5550 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg); in selectBuildVector()
5569 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS); in selectVectorLoadIntrinsic()
5585 auto Vec = MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(Idx)}, {}) in selectVectorLoadIntrinsic()
6049 if (OffsetOpc != TargetOpcode::G_SHL && OffsetOpc != TargetOpcode::G_MUL) { in selectExtendedSHL()
6051 if (OffsetOpc != TargetOpcode::G_ZEXT || !WantsExt) in selectExtendedSHL()
6058 if (OffsetOpc != TargetOpcode::G_SHL && OffsetOpc != TargetOpcode::G_MUL) in selectExtendedSHL()
6077 if (OffsetOpc == TargetOpcode::G_SHL) in selectExtendedSHL()
6093 if (OffsetOpc == TargetOpcode::G_MUL) { in selectExtendedSHL()
6171 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
6199 if (Gep->getOpcode() != TargetOpcode::G_PTR_ADD) in selectAddrModeRegisterOffset()
6232 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeXRO()
6305 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeWRO()
6384 if (RHS->getOpcode() != TargetOpcode::G_CONSTANT) in selectAddrModeUnscaled()
6452 if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) { in selectAddrModeIndexed()
6476 if (LHSDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) in selectAddrModeIndexed()
6506 case TargetOpcode::G_SHL: in getShiftTypeForInst()
6508 case TargetOpcode::G_LSHR: in getShiftTypeForInst()
6510 case TargetOpcode::G_ASHR: in getShiftTypeForInst()
6512 case TargetOpcode::G_ROTR: in getShiftTypeForInst()
6562 if (Opc == TargetOpcode::G_SEXT || Opc == TargetOpcode::G_SEXT_INREG) { in getExtendTypeForInst()
6564 if (Opc == TargetOpcode::G_SEXT) in getExtendTypeForInst()
6581 if (Opc == TargetOpcode::G_ZEXT || Opc == TargetOpcode::G_ANYEXT) { in getExtendTypeForInst()
6598 if (Opc != TargetOpcode::G_AND) in getExtendTypeForInst()
6653 if (RootDef->getOpcode() == TargetOpcode::G_SHL) { in selectArithExtendedRegister()
6704 assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderTruncImm()
6714 assert(I.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderLogicalImm32()
6723 assert(I.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderLogicalImm64()
6733 assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && in renderFPImm16()
6742 assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && in renderFPImm32()
6751 assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && in renderFPImm64()
6759 assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && in renderFPImm32SIMDModImmType4()
6789 case TargetOpcode::COPY: in isDef32()
6790 case TargetOpcode::G_BITCAST: in isDef32()
6791 case TargetOpcode::G_TRUNC: in isDef32()
6792 case TargetOpcode::G_PHI: in isDef32()
6802 assert(MI.getOpcode() == TargetOpcode::G_PHI && "Expected a G_PHI"); in fixupPHIOpBanks()
6839 if (MI.getOpcode() == TargetOpcode::G_PHI) in processPHIs()