302   MachineInstr *emitConjunction(Register Val, AArch64CC::CondCode &OutCC,
307                                           AArch64CC::CondCode OutCC,
309   MachineInstr *emitConjunctionRec(Register Val, AArch64CC::CondCode &OutCC,
4817     AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC,  in emitConditionalComparison()  argument
4841   AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);  in emitConditionalComparison()
4850     Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp,  in emitConjunctionRec()  argument
4863       OutCC = changeICMPPredToAArch64CC(CC);  in emitConjunctionRec()
4867       changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);  in emitConjunctionRec()
4891     return emitConditionalComparison(LHS, RHS, CC, Predicate, OutCC, MIB);  in emitConjunctionRec()
4957       LHS, OutCC, NegateL, CmpR->getOperand(0).getReg(), RHSCC, MIB);  in emitConjunctionRec()
4959     OutCC = AArch64CC::getInvertedCondCode(OutCC);  in emitConjunctionRec()
4964     Register Val, AArch64CC::CondCode &OutCC, MachineIRBuilder &MIB) const {  in emitConjunction()  argument
4970   return emitConjunctionRec(Val, OutCC, false, Register(), AArch64CC::AL, MIB);  in emitConjunction()