1515   static const unsigned OpcTable[2][2] = {{AArch64::TBZX, AArch64::TBNZX},  in emitTestBit()  local
1517   unsigned Opc = OpcTable[UseWReg][IsNegative];  in emitTestBit()
1578   static const unsigned OpcTable[2][2] = {{AArch64::CBZW, AArch64::CBZX},  in emitCBZ()  local
1580   unsigned Opc = OpcTable[IsNegative][Width == 64];  in emitCBZ()
2414     static const unsigned OpcTable[2][2] = {  in select()  local
2419     unsigned Opc = OpcTable[IsSigned][Size == 64];  in select()
3849   static const unsigned OpcTable[4][4][9] = {  in selectVectorICmp()  local
3909   unsigned Opc = OpcTable[EltIdx][NumEltsIdx][PredIdx];  in selectVectorICmp()
4487   const std::array<std::array<unsigned, 2>, 5> OpcTable{  in emitADD()  local
4493   return emitAddSub(OpcTable, DefReg, LHS, RHS, MIRBuilder);  in emitADD()
4500   const std::array<std::array<unsigned, 2>, 5> OpcTable{  in emitADDS()  local
4506   return emitAddSub(OpcTable, Dst, LHS, RHS, MIRBuilder);  in emitADDS()
4513   const std::array<std::array<unsigned, 2>, 5> OpcTable{  in emitSUBS()  local
4519   return emitAddSub(OpcTable, Dst, LHS, RHS, MIRBuilder);  in emitSUBS()
4539   const unsigned OpcTable[3][2] = {{AArch64::ANDSXri, AArch64::ANDSWri},  in emitTST()  local
4548       auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {Ty}, {LHS});  in emitTST()
4556     return emitInstr(OpcTable[1][Is32Bit], {Ty}, {LHS}, MIRBuilder, Fns);  in emitTST()
4557   return emitInstr(OpcTable[2][Is32Bit], {Ty}, {LHS, RHS}, MIRBuilder);  in emitTST()
4722   static const unsigned OpcTable[2] = {AArch64::CSINCWr, AArch64::CSINCXr};  in emitCSINC()  local
4723   unsigned Opc = OpcTable[Size == 64];  in emitCSINC()