Lines Matching refs:MIB
82 MIB.setMF(MF); in setupMF()
124 MachineIRBuilder &MIB) const;
126 MachineIRBuilder &MIB) const;
128 MachineIRBuilder &MIB) const;
131 MachineIRBuilder &MIB) const;
303 MachineIRBuilder &MIB) const;
308 MachineIRBuilder &MIB) const;
312 MachineIRBuilder &MIB) const;
319 MachineIRBuilder &MIB) const;
324 MachineIRBuilder &MIB) const;
424 MachineIRBuilder &MIB) const;
428 void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
430 void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
432 void renderLogicalImm64(MachineInstrBuilder &MIB, const MachineInstr &I,
434 void renderFPImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
436 void renderFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
438 void renderFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
440 void renderFPImm32SIMDModImmType4(MachineInstrBuilder &MIB,
475 MachineIRBuilder MIB; member in __anon0f33cebd0111::AArch64InstructionSelector
642 const unsigned SubRegs[], MachineIRBuilder &MIB) { in createTuple() argument
648 const TargetRegisterInfo *TRI = MIB.getMF().getSubtarget().getRegisterInfo(); in createTuple()
651 MIB.buildInstr(TargetOpcode::REG_SEQUENCE, {DesiredClass}, {}); in createTuple()
660 static Register createDTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createDTuple() argument
665 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createDTuple()
669 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() argument
674 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createQTuple()
866 MachineIRBuilder MIB(I); in copySubReg() local
868 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg); in copySubReg()
948 MachineIRBuilder MIB(I); in selectCopy() local
949 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
1080 MachineIRBuilder &MIB) const { in emitSelect()
1081 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitSelect()
1094 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1243 auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1493 MachineIRBuilder &MIB) const { in emitTestBit()
1497 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitTestBit()
1513 MIB); in emitTestBit()
1519 MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); in emitTestBit()
1526 MachineIRBuilder &MIB) const { in tryOptAndIntoCompareBranch()
1550 AndInst.getOperand(2).getReg(), *MIB.getMRI()); in tryOptAndIntoCompareBranch()
1561 emitTestBit(TestReg, Bit, Invert, DstMBB, MIB); in tryOptAndIntoCompareBranch()
1568 MachineIRBuilder &MIB) const { in emitCBZ()
1570 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitCBZ()
1581 auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); in emitCBZ()
1587 MachineInstr &I, MachineInstr &FCmp, MachineIRBuilder &MIB) const { in selectCompareBranchFedByFCmp()
1593 emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, in selectCompareBranchFedByFCmp()
1598 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1600 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1606 MachineInstr &I, MachineInstr &ICmp, MachineIRBuilder &MIB) const { in tryOptCompareBranchFedByICmp()
1617 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptCompareBranchFedByICmp()
1640 emitTestBit(LHS, Bit, /*IsNegative = */ false, DestMBB, MIB); in tryOptCompareBranchFedByICmp()
1649 emitTestBit(LHS, Bit, /*IsNegative = */ true, DestMBB, MIB); in tryOptCompareBranchFedByICmp()
1673 *AndInst, /*Invert = */ Pred == CmpInst::ICMP_NE, DestMBB, MIB)) { in tryOptCompareBranchFedByICmp()
1681 emitCBZ(LHS, /*IsNegative = */ Pred == CmpInst::ICMP_NE, DestMBB, MIB); in tryOptCompareBranchFedByICmp()
1692 MachineInstr &I, MachineInstr &ICmp, MachineIRBuilder &MIB) const { in selectCompareBranchFedByICmp()
1695 if (tryOptCompareBranchFedByICmp(I, ICmp, MIB)) in selectCompareBranchFedByICmp()
1701 emitIntegerCompare(ICmp.getOperand(2), ICmp.getOperand(3), PredOp, MIB); in selectCompareBranchFedByICmp()
1704 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB); in selectCompareBranchFedByICmp()
1717 return selectCompareBranchFedByFCmp(I, *CCMI, MIB); in selectCompareBranch()
1719 return selectCompareBranchFedByICmp(I, *CCMI, MIB); in selectCompareBranch()
1726 I.getOperand(1).getMBB(), MIB); in selectCompareBranch()
1733 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
1735 auto Bcc = MIB.buildInstr(AArch64::Bcc) in selectCompareBranch()
1820 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg}); in selectVectorSHL()
1881 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg}); in selectVectorAshrLshr()
1883 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg}); in selectVectorAshrLshr()
1901 auto MIB = in selectVaStartDarwin() local
1908 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
1910 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui)) in selectVaStartDarwin()
1916 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
1927 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {}); in materializeLargeCMVal()
1939 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
1971 auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp); in preISelLower()
1998 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower()
2050 auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg); in convertPtrAddToAdd()
2099 MIB.buildInstr(Is64Bit ? AArch64::UBFMXri : AArch64::UBFMWri, in earlySelectSHL()
2175 if (!emitConstantVector(Dst, CV, MIB, MRI)) in earlySelect()
2269 MIB.setInstrAndDebugLoc(I); in earlySelect()
2271 /*RHS=*/Cmp->getOperand(3), PredOp, MIB); in earlySelect()
2272 emitCSINC(/*Dst=*/AddDst, /*Src =*/AddLHS, /*Src2=*/AddLHS, InvCC, MIB); in earlySelect()
2306 emitInstr(Opc, {Dst}, {MaskSrc, ShiftSrc, Immr, Imms}, MIB); in earlySelect()
2340 MIB.setInstrAndDebugLoc(I); in select()
2429 MIB.buildInstr(Opc, {I.getOperand(0)}, {I.getOperand(1)}) in select()
2461 auto MovAddr = MIB.buildInstr(AArch64::MOVaddr, {I.getOperand(0)}, {}) in select()
2577 auto *LoadMI = emitLoadFromConstantPool(FPImm, MIB); in select()
2582 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()}); in select()
2595 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator())); in select()
2596 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
2647 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}) in select()
2657 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
2675 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator())); in select()
2676 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in select()
2755 MachineInstrBuilder MIB(MF, I); in select() local
2756 MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(), in select()
2804 MIB.buildInstr(TargetOpcode::COPY, {NewVal}, {}) in select()
2838 auto Copy = MIB.buildInstr(TargetOpcode::COPY, {MemTy}, {}) in select()
2858 MIB.setInsertPt(MIB.getMBB(), std::next(LdSt.getIterator())); in select()
2859 MIB.buildInstr(AArch64::SUBREG_TO_REG, {OldDst}, {}) in select()
2865 MIB.setInstr(LdSt); in select()
2888 auto NewInst = MIB.buildInstr(NewOpc, {}, {}, I.getFlags()); in select()
2931 MIB.setInsertPt(MIB.getMBB(), std::next(LoadStore->getIterator())); in select()
2932 MIB.buildInstr(AArch64::SUBREG_TO_REG, {DstReg}, {}) in select()
2994 auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {}) in select()
3024 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2), MIB); in select()
3034 I.getOperand(2), I.getOperand(3), MIB); in select()
3042 getInvertedCondCode(OpAndCC.second), MIB); in select()
3120 DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB); in select()
3248 MIB.buildInstr(AArch64::ORRWrs, {OrDst}, {ZReg, SrcReg}).addImm(0); in select()
3252 MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) in select()
3283 SrcReg = MIB.buildInstr(AArch64::SUBREG_TO_REG, in select()
3291 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMXri : AArch64::UBFMXri, in select()
3296 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMWri : AArch64::UBFMWri, in select()
3354 auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg}) in select()
3357 if (!emitSelect(Sel.getReg(0), TReg, FReg, AArch64CC::NE, MIB)) in select()
3375 emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1), MIB); in select()
3377 /*Src2=*/AArch64::WZR, InvCC, MIB); in select()
3385 if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(), MIB, in select()
3387 !emitCSetForFCmp(I.getOperand(0).getReg(), Pred, MIB)) in select()
3491 auto AddP = MIB.buildInstr(AArch64::ADDPv2i32, {&AArch64::FPR64RegClass}, in selectReduction()
3493 auto Copy = MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}) in selectReduction()
3569 MIB.buildCopy(DstPtrCopy, DstPtr); in selectMOPS()
3570 MIB.buildCopy(SrcValCopy, SrcOrVal); in selectMOPS()
3571 MIB.buildCopy(SizeCopy, Size); in selectMOPS()
3580 MIB.buildInstr(Mopcode, {DefDstPtr, DefSize}, in selectMOPS()
3584 MIB.buildInstr(Mopcode, {DefDstPtr, DefSrcPtr, DefSize}, in selectMOPS()
3603 auto JumpTableInst = MIB.buildInstr(AArch64::JumpTableDest32, in selectBrJT()
3607 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
3621 MIB.buildInstr(AArch64::MOVaddrJT, {DstReg}, {}) in selectJumpTable()
3641 MIB.buildInstr(AArch64::LOADgot, {&AArch64::GPR64commonRegClass}, {}) in selectTLSGlobalValue()
3644 auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass}, in selectTLSGlobalValue()
3648 MIB.buildCopy(Register(AArch64::X0), LoadGOT.getReg(0)); in selectTLSGlobalValue()
3652 MIB.buildInstr(getBLRCallOpcode(MF), {}, {Load}) in selectTLSGlobalValue()
3657 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0)); in selectTLSGlobalValue()
3930 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg}); in selectVectorICmp()
3935 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp}); in selectVectorICmp()
3938 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
3990 auto Tmp = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstTy}, {}); in selectMergeValues()
3992 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB); in selectMergeValues()
3996 Src2Reg, /* LaneIdx */ 1, RB, MIB); in selectMergeValues()
4161 LaneIdx, MIB); in selectExtractElt()
4189 emitExtractVectorElt(Dst, DstRB, NarrowTy, SrcReg, OpIdx, MIB); in selectSplitVectorUnmerge()
4286 auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {}) in selectUnmergeValues()
4324 MachineInstr *ConcatMI = emitVectorConcat(Dst, Op1, Op2, MIB); in selectConcatVectors()
4818 MachineIRBuilder &MIB) const { in emitConditionalComparison()
4820 auto &MRI = *MIB.getMRI(); in emitConditionalComparison()
4844 MIB.buildInstr(CCmpOpc, {}, {LHS, RHS}).addImm(NZCV).addImm(Predicate); in emitConditionalComparison()
4851 AArch64CC::CondCode Predicate, MachineIRBuilder &MIB) const { in emitConjunctionRec()
4853 auto &MRI = *MIB.getMRI(); in emitConjunctionRec()
4873 ExtraCmp = emitFPCompare(LHS, RHS, MIB, CC); in emitConjunctionRec()
4876 emitConditionalComparison(LHS, RHS, CC, Predicate, ExtraCC, MIB); in emitConjunctionRec()
4886 return emitSUBS(Dst, Cmp->getOperand(2), Cmp->getOperand(3), MIB); in emitConjunctionRec()
4888 Cmp->getOperand(3).getReg(), MIB); in emitConjunctionRec()
4891 return emitConditionalComparison(LHS, RHS, CC, Predicate, OutCC, MIB); in emitConjunctionRec()
4953 emitConjunctionRec(RHS, RHSCC, NegateR, CCOp, Predicate, MIB); in emitConjunctionRec()
4957 LHS, OutCC, NegateL, CmpR->getOperand(0).getReg(), RHSCC, MIB); in emitConjunctionRec()
4964 Register Val, AArch64CC::CondCode &OutCC, MachineIRBuilder &MIB) const { in emitConjunction()
4968 *MIB.getMRI())) in emitConjunction()
4970 return emitConjunctionRec(Val, OutCC, false, Register(), AArch64CC::AL, MIB); in emitConjunction()
4976 MachineInstr *ConjMI = emitConjunction(SelI.getCondReg(), AArch64CC, MIB); in tryOptSelectConjunction()
4980 emitSelect(SelI.getReg(0), SelI.getTrueReg(), SelI.getFalseReg(), AArch64CC, MIB); in tryOptSelectConjunction()
4986 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptSelect()
5033 CondDef->getOperand(1), MIB); in tryOptSelect()
5049 CondDef->getOperand(3).getReg(), MIB)) { in tryOptSelect()
5057 I.getOperand(3).getReg(), CondCode, MIB); in tryOptSelect()
5163 MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIB); in selectShuffleVector()
5172 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIB); in selectShuffleVector()
5180 IndexLoad->getOperand(0).getReg(), MIB); in selectShuffleVector()
5182 auto TBL1 = MIB.buildInstr( in selectShuffleVector()
5188 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in selectShuffleVector()
5198 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5199 auto TBL2 = MIB.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0)}, in selectShuffleVector()
5262 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, Src0, MIB); in selectUSMovFromExtend()
5288 MIB.buildInstr(Opcode, {NewReg}, {Src0}).addImm(Lane); in selectUSMovFromExtend()
5289 ExtI = MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) in selectUSMovFromExtend()
5295 ExtI = MIB.buildInstr(Opcode, {DefReg}, {Src0}).addImm(Lane); in selectUSMovFromExtend()
5334 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
5344 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()
5364 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}) in selectInsertElt()
5440 if (!emitConstantVector(I.getOperand(0).getReg(), CV, MIB, MRI)) in tryOptConstantBuildVec()
5477 auto SubregToReg = MIB.buildInstr(AArch64::SUBREG_TO_REG, {Dst}, {}) in tryOptBuildVecToSubregToReg()
5507 I.getOperand(1).getReg(), MIB); in selectBuildVector()
5521 MIB); in selectBuildVector()
5550 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg); in selectBuildVector()
5572 auto &MRI = *MIB.getMRI(); in selectVectorLoadIntrinsic()
5580 auto Load = MIB.buildInstr(Opc, {Ty}, {Ptr}); in selectVectorLoadIntrinsic()
5585 auto Vec = MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(Idx)}, {}) in selectVectorLoadIntrinsic()
5611 auto NewI = MIB.buildInstr( in selectIntrinsicWithSideEffects()
5620 MIB.buildInstr(AArch64::BRK, {}, {}).addImm(1); in selectIntrinsicWithSideEffects()
5623 MIB.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000); in selectIntrinsicWithSideEffects()
5626 MIB.buildInstr(AArch64::BRK, {}, {}) in selectIntrinsicWithSideEffects()
5702 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
5703 : createDTuple(Regs, MIB); in selectIntrinsicWithSideEffects()
5704 auto Store = MIB.buildInstr(Opc, {}, {Tuple, Ptr}); in selectIntrinsicWithSideEffects()
5733 auto Memset = MIB.buildInstr(AArch64::MOPSMemorySetTaggingPseudo, in selectIntrinsicWithSideEffects()
5765 MIB.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
5776 auto SHA1Inst = MIB.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg}); in selectIntrinsic()
5783 MIB.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
5807 auto PAC = MIB.buildInstr(Opcode, {DstReg}, {ValReg}); in selectIntrinsic()
5837 MIB.buildInstr(AArch64::XPACI, {DstReg}, {MFReturnAddr}); in selectIntrinsic()
5839 MIB.buildCopy({Register(AArch64::LR)}, {MFReturnAddr}); in selectIntrinsic()
5840 MIB.buildInstr(AArch64::XPACLRI); in selectIntrinsic()
5841 MIB.buildCopy({DstReg}, {Register(AArch64::LR)}); in selectIntrinsic()
5853 MIB.buildInstr(AArch64::LDRXui, {NextFrame}, {FrameAddr}).addImm(0); in selectIntrinsic()
5859 MIB.buildCopy({DstReg}, {FrameAddr}); in selectIntrinsic()
5865 MIB.buildInstr(AArch64::LDRXui, {TmpReg}, {FrameAddr}).addImm(1); in selectIntrinsic()
5866 MIB.buildInstr(AArch64::XPACI, {DstReg}, {TmpReg}); in selectIntrinsic()
5868 MIB.buildInstr(AArch64::LDRXui, {Register(AArch64::LR)}, {FrameAddr}) in selectIntrinsic()
5870 MIB.buildInstr(AArch64::XPACLRI); in selectIntrinsic()
5871 MIB.buildCopy({DstReg}, {Register(AArch64::LR)}); in selectIntrinsic()
5879 auto Sub = MIB.buildInstr(AArch64::SUBXri, {I.getOperand(0).getReg()}, in selectIntrinsic()
5899 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_32()
5908 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_32()
5917 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_64()
5926 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_64()
5948 [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed); }, in select12BitValueWithLeftShift()
5949 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShVal); }, in select12BitValueWithLeftShift()
6127 MachineIRBuilder MIB(*MRI.getVRegDef(Root.getReg())); in selectExtendedSHL() local
6128 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); in selectExtendedSHL()
6133 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(Base.getReg()); }, in selectExtendedSHL()
6134 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
6135 [=](MachineInstrBuilder &MIB) { in selectExtendedSHL()
6138 MIB.addImm(SignExtend); in selectExtendedSHL()
6139 MIB.addImm(1); in selectExtendedSHL()
6209 return {{[=](MachineInstrBuilder &MIB) { in selectAddrModeRegisterOffset()
6210 MIB.addUse(Gep->getOperand(1).getReg()); in selectAddrModeRegisterOffset()
6212 [=](MachineInstrBuilder &MIB) { in selectAddrModeRegisterOffset()
6213 MIB.addUse(Gep->getOperand(2).getReg()); in selectAddrModeRegisterOffset()
6215 [=](MachineInstrBuilder &MIB) { in selectAddrModeRegisterOffset()
6218 MIB.addImm(0); in selectAddrModeRegisterOffset()
6219 MIB.addImm(0); in selectAddrModeRegisterOffset()
6347 MachineIRBuilder MIB(*PtrAdd); in selectAddrModeWRO() local
6349 AArch64::GPR32RegClass, MIB); in selectAddrModeWRO()
6353 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(LHS.getReg()); }, in selectAddrModeWRO()
6354 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
6355 [=](MachineInstrBuilder &MIB) { in selectAddrModeWRO()
6356 MIB.addImm(SignExtend); in selectAddrModeWRO()
6357 MIB.addImm(0); in selectAddrModeWRO()
6398 [=](MachineInstrBuilder &MIB) { MIB.add(Base); }, in selectAddrModeUnscaled()
6399 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); }, in selectAddrModeUnscaled()
6431 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(AdrpReg); }, in tryFoldAddLowIntoImm()
6432 [=](MachineInstrBuilder &MIB) { in tryFoldAddLowIntoImm()
6433 MIB.addGlobalAddress(GV, Offset, in tryFoldAddLowIntoImm()
6454 [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }, in selectAddrModeIndexed()
6455 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, in selectAddrModeIndexed()
6478 [=](MachineInstrBuilder &MIB) { MIB.add(LHSDef->getOperand(1)); }, in selectAddrModeIndexed()
6479 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC >> Scale); }, in selectAddrModeIndexed()
6483 [=](MachineInstrBuilder &MIB) { MIB.add(LHS); }, in selectAddrModeIndexed()
6484 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC >> Scale); }, in selectAddrModeIndexed()
6495 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectAddrModeIndexed()
6496 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, in selectAddrModeIndexed()
6553 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); }, in selectShiftedRegister()
6554 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
6618 Register Reg, const TargetRegisterClass &RC, MachineIRBuilder &MIB) const { in moveScalarRegClass()
6619 MachineRegisterInfo &MRI = *MIB.getMRI(); in moveScalarRegClass()
6627 auto Copy = MIB.buildCopy({&RC}, {Reg}); in moveScalarRegClass()
6691 MachineIRBuilder MIB(*RootDef); in selectArithExtendedRegister() local
6692 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
6694 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()
6695 [=](MachineInstrBuilder &MIB) { in selectArithExtendedRegister()
6696 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
6700 void AArch64InstructionSelector::renderTruncImm(MachineInstrBuilder &MIB, in renderTruncImm() argument
6709 MIB.addImm(*CstVal); in renderTruncImm()
6713 MachineInstrBuilder &MIB, const MachineInstr &I, int OpIdx) const { in renderLogicalImm32() argument
6718 MIB.addImm(Enc); in renderLogicalImm32()
6722 MachineInstrBuilder &MIB, const MachineInstr &I, int OpIdx) const { in renderLogicalImm64() argument
6727 MIB.addImm(Enc); in renderLogicalImm64()
6730 void AArch64InstructionSelector::renderFPImm16(MachineInstrBuilder &MIB, in renderFPImm16() argument
6735 MIB.addImm( in renderFPImm16()
6739 void AArch64InstructionSelector::renderFPImm32(MachineInstrBuilder &MIB, in renderFPImm32() argument
6744 MIB.addImm( in renderFPImm32()
6748 void AArch64InstructionSelector::renderFPImm64(MachineInstrBuilder &MIB, in renderFPImm64() argument
6753 MIB.addImm( in renderFPImm64()
6758 MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { in renderFPImm32SIMDModImmType4() argument
6761 MIB.addImm(AArch64_AM::encodeAdvSIMDModImmType4(MI.getOperand(1) in renderFPImm32SIMDModImmType4()
6806 MachineIRBuilder MIB(MI); in fixupPHIOpBanks() local
6825 MIB.setInsertPt(*OpDef->getParent(), InsertPt); in fixupPHIOpBanks()
6826 auto Copy = MIB.buildCopy(Ty, OpReg); in fixupPHIOpBanks()