143                                    const TargetRegisterClass *DstRC,
920   const TargetRegisterClass *DstRC;  in selectCopy()  local
921   std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);  in selectCopy()
923   if (!DstRC) {  in selectCopy()
938     unsigned DstSize = TRI.getRegSizeInBits(*DstRC);  in selectCopy()
946       getSubRegForClass(DstRC, TRI, SubReg);  in selectCopy()
950       copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg);  in selectCopy()
957       copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg);  in selectCopy()
983   if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {  in selectCopy()
3079       const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);  in select()  local
3080       if (!DstRC)  in select()
3088           !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {  in select()
3093       if (DstRC == SrcRC) {  in select()
3099       } else if (DstRC == &AArch64::GPR32RegClass &&  in select()
3404     const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);  in select()  local
3405     RBI.constrainGenericRegister(DstReg, *DstRC, MRI);  in select()
3946     unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,  in emitScalarToVector()  argument
3948   auto Undef = MIRBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstRC}, {});  in emitScalarToVector()
3953             .buildInstr(TargetOpcode::INSERT_SUBREG, {DstRC}, {Undef, Scalar})  in emitScalarToVector()
4011   auto *DstRC = &AArch64::GPR64RegClass;  in selectMergeValues()  local
4012   Register SubToRegDef = MRI.createVirtualRegister(DstRC);  in selectMergeValues()
4019   Register SubToRegDef2 = MRI.createVirtualRegister(DstRC);  in selectMergeValues()
4082   const TargetRegisterClass *DstRC =  in emitExtractVectorElt()  local
4084   if (!DstRC) {  in emitExtractVectorElt()
4101     DstReg = MRI.createVirtualRegister(DstRC);  in emitExtractVectorElt()
4106     RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);  in emitExtractVectorElt()
4126   RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);  in emitExtractVectorElt()
4678   const TargetRegisterClass *DstRC =  in emitVectorConcat()  local
4682       emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder);  in emitVectorConcat()
4684       emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder);  in emitVectorConcat()
4696     Dst = MRI.createVirtualRegister(DstRC);  in emitVectorConcat()
5211   const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;  in emitLaneInsert()  local
5216     DstReg = MRI.createVirtualRegister(DstRC);  in emitLaneInsert()
5222     auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder);  in emitLaneInsert()
5471   const TargetRegisterClass *DstRC =  in tryOptBuildVecToSubregToReg()  local
5473   if (!DstRC)  in tryOptBuildVecToSubregToReg()
5483   return RBI.constrainGenericRegister(Dst, *DstRC, MRI);  in tryOptBuildVecToSubregToReg()
5504   const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;  in selectBuildVector()  local
5506       emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC,  in selectBuildVector()