Lines Matching refs:getShiftExtendAmount

717   unsigned getShiftExtendAmount() const {  in getShiftExtendAmount()  function in __anone48315620111::AArch64Operand
1220 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8); in isSVEDataVectorRegWithShiftExtend()
1284 getShiftExtendAmount() == Log2_32(ExtWidth / 8)) in isGPR64WithShiftExtend()
1384 getShiftExtendAmount() <= 4; in isExtend()
1403 getShiftExtendAmount() <= 4; in isExtendLSL64()
1411 (getShiftExtendAmount() == Log2_32(Width / 8) || in isMemXExtend()
1412 getShiftExtendAmount() == 0); in isMemXExtend()
1420 (getShiftExtendAmount() == Log2_32(Width / 8) || in isMemWExtend()
1421 getShiftExtendAmount() == 0); in isMemWExtend()
1432 ST == AArch64_AM::ASR) && getShiftExtendAmount() < width; in isArithmeticShifter()
1444 getShiftExtendAmount() < width; in isLogicalShifter()
1455 uint64_t Val = getShiftExtendAmount(); in isMovImm32Shifter()
1467 uint64_t Val = getShiftExtendAmount(); in isMovImm64Shifter()
1476 unsigned Shift = getShiftExtendAmount(); in isLogicalVecShifter()
1486 unsigned Shift = getShiftExtendAmount(); in isLogicalVecHalfWordShifter()
1496 unsigned Shift = getShiftExtendAmount(); in isMoveVecShifter()
1892 AArch64_AM::getShifterImm(getShiftExtendType(), getShiftExtendAmount()); in addShifterOperands()
1900 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); in addExtendOperands()
1908 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); in addExtend64Operands()
1917 Inst.addOperand(MCOperand::createImm(getShiftExtendAmount() != 0)); in addMemExtendOperands()
2314 if (!getShiftExtendAmount() && !hasShiftExtendAmount()) in print()
2319 << getShiftExtendAmount(); in print()
4165 Ext->getShiftExtendType(), Ext->getShiftExtendAmount(), in tryParseGPROperand()
7024 getContext(), Ext->getShiftExtendType(), Ext->getShiftExtendAmount(), in tryParseSVEDataVector()