Lines Matching refs:ElementWidth
363 int ElementWidth; member
388 unsigned ElementWidth; member
400 unsigned ElementWidth; member
631 return MatrixReg.ElementWidth; in getMatrixElementWidth()
1187 template <int ElementWidth, unsigned Class>
1192 if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth)) in isSVEPredicateVectorRegOfWidth()
1198 template <int ElementWidth, unsigned Class>
1203 if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth) in isSVEDataVectorRegOfWidth()
1209 template <int ElementWidth, unsigned Class,
1213 auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>(); in isSVEDataVectorRegWithShiftExtend()
1299 unsigned ElementWidth>
1307 if (VectorList.ElementWidth != ElementWidth) in isTypedVectorList()
1988 Op->Reg.ElementWidth = 0; in CreateReg()
1999 CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth, in CreateVectorReg() argument
2009 Op->Reg.ElementWidth = ElementWidth; in CreateVectorReg()
2015 unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E, in CreateVectorList() argument
2021 Op->VectorList.ElementWidth = ElementWidth; in CreateVectorList()
2047 const unsigned ElementWidth) { in ComputeRegsForAlias() argument
2066 if (ElementWidth == 64) in ComputeRegsForAlias()
2069 std::vector<unsigned> Regs = RegMap[std::make_pair(ElementWidth, Reg)]; in ComputeRegsForAlias()
2196 CreateMatrixRegister(unsigned RegNum, unsigned ElementWidth, MatrixKind Kind, in CreateMatrixRegister() argument
2200 Op->MatrixReg.ElementWidth = ElementWidth; in CreateMatrixRegister()
3174 unsigned ElementWidth = KindRes->second; in tryParseMatrixRegister() local
3179 Reg, ElementWidth, Kind, S, getLoc(), getContext())); in tryParseMatrixRegister()
3640 unsigned ElementWidth = KindRes->second; in tryParseNeonVectorRegister() local
3642 AArch64Operand::CreateVectorReg(Reg, RegKind::NeonVector, ElementWidth, in tryParseNeonVectorRegister()
3729 unsigned ElementWidth = KindRes->second; in tryParseSVEPredicateVector() local
3731 RegNum, RegKind::SVEPredicateVector, ElementWidth, S, in tryParseSVEPredicateVector()
3867 auto ParseMatrixTile = [this](unsigned &Reg, unsigned &ElementWidth) { in tryParseMatrixTileList() argument
3884 ElementWidth = KindRes->second; in tryParseMatrixTileList()
3915 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
3916 auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth); in tryParseMatrixTileList()
3927 AArch64Operand::ComputeRegsForAlias(FirstReg, DRegs, ElementWidth); in tryParseMatrixTileList()
3940 if (ElementWidth != NextElementWidth) { in tryParseMatrixTileList()
3952 AArch64Operand::ComputeRegsForAlias(Reg, DRegs, ElementWidth); in tryParseMatrixTileList()
4080 unsigned ElementWidth = 0; in tryParseVectorList() local
4083 std::tie(NumElements, ElementWidth) = *VK; in tryParseVectorList()
4087 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), in tryParseVectorList()
6999 unsigned ElementWidth = KindRes->second; in tryParseSVEDataVector() local
7004 RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext())); in tryParseSVEDataVector()
7023 RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(), in tryParseSVEDataVector()