Lines Matching refs:MF
70 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { in getCalleeSavedRegs()
71 assert(MF && "Invalid MachineFunction pointer."); in getCalleeSavedRegs()
73 if (MF->getFunction().getCallingConv() == CallingConv::GHC) in getCalleeSavedRegs()
77 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) in getCalleeSavedRegs()
82 if (MF->getSubtarget<AArch64Subtarget>().isTargetDarwin()) in getCalleeSavedRegs()
83 return getDarwinCalleeSavedRegs(MF); in getCalleeSavedRegs()
85 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check) in getCalleeSavedRegs()
87 if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows()) in getCalleeSavedRegs()
89 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall) in getCalleeSavedRegs()
91 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall) in getCalleeSavedRegs()
93 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() in getCalleeSavedRegs()
95 MF->getFunction().getAttributes().hasAttrSomewhere( in getCalleeSavedRegs()
98 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail) in getCalleeSavedRegs()
100 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost) in getCalleeSavedRegs()
102 if (MF->getFunction().getCallingConv() == CallingConv::Win64) in getCalleeSavedRegs()
106 if (MF->getInfo<AArch64FunctionInfo>()->isSVECC()) in getCalleeSavedRegs()
112 AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const { in getDarwinCalleeSavedRegs()
113 assert(MF && "Invalid MachineFunction pointer."); in getDarwinCalleeSavedRegs()
114 assert(MF->getSubtarget<AArch64Subtarget>().isTargetDarwin() && in getDarwinCalleeSavedRegs()
117 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check) in getDarwinCalleeSavedRegs()
120 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall) in getDarwinCalleeSavedRegs()
122 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall) in getDarwinCalleeSavedRegs()
125 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS) in getDarwinCalleeSavedRegs()
126 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() in getDarwinCalleeSavedRegs()
129 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() in getDarwinCalleeSavedRegs()
131 MF->getFunction().getAttributes().hasAttrSomewhere( in getDarwinCalleeSavedRegs()
134 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail) in getDarwinCalleeSavedRegs()
136 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost) in getDarwinCalleeSavedRegs()
142 const MachineFunction *MF) const { in getCalleeSavedRegsViaCopy()
143 assert(MF && "Invalid MachineFunction pointer."); in getCalleeSavedRegsViaCopy()
144 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in getCalleeSavedRegsViaCopy()
145 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()) in getCalleeSavedRegsViaCopy()
151 MachineFunction &MF) const { in UpdateCustomCalleeSavedRegs()
152 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF); in UpdateCustomCalleeSavedRegs()
158 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) { in UpdateCustomCalleeSavedRegs()
164 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs); in UpdateCustomCalleeSavedRegs()
181 AArch64RegisterInfo::getDarwinCallPreservedMask(const MachineFunction &MF, in getDarwinCallPreservedMask() argument
183 assert(MF.getSubtarget<AArch64Subtarget>().isTargetDarwin() && in getDarwinCallPreservedMask()
196 if (MF.getSubtarget<AArch64Subtarget>() in getDarwinCallPreservedMask()
199 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) in getDarwinCallPreservedMask()
209 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, in getCallPreservedMask() argument
211 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack); in getCallPreservedMask()
219 if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) { in getCallPreservedMask()
222 return getDarwinCallPreservedMask(MF, CC); in getCallPreservedMask()
232 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering() in getCallPreservedMask()
234 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) in getCallPreservedMask()
250 const MachineFunction &MF) const { in getCustomEHPadPreservedMask()
251 if (MF.getSubtarget<AArch64Subtarget>().isTargetLinux()) in getCustomEHPadPreservedMask()
265 void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF, in UpdateCustomCallPreservedMask() argument
267 uint32_t *UpdatedMask = MF.allocateRegMask(); in UpdateCustomCallPreservedMask()
272 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) { in UpdateCustomCallPreservedMask()
290 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, in getThisReturnPreservedMask() argument
300 if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) in getThisReturnPreservedMask()
310 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()
311 const AArch64FrameLowering *TFI = getFrameLowering(MF); in getReservedRegs()
318 if (TFI->hasFP(MF) || TT.isOSDarwin()) in getReservedRegs()
322 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i)) in getReservedRegs()
326 if (hasBasePointer(MF)) in getReservedRegs()
330 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening)) in getReservedRegs()
334 if (MF.getSubtarget<AArch64Subtarget>().hasSME()) { in getReservedRegs()
344 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, in isReservedReg() argument
346 return getReservedRegs(MF)[Reg]; in isReservedReg()
349 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const { in isAnyArgRegReserved()
350 return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) { in isAnyArgRegReserved()
351 return isReservedReg(MF, r); in isAnyArgRegReserved()
356 const MachineFunction &MF) const { in emitReservedArgRegCallError()
357 const Function &F = MF.getFunction(); in emitReservedArgRegCallError()
362 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF, in isAsmClobberable() argument
364 return !isReservedReg(MF, PhysReg); in isAsmClobberable()
372 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF, in getPointerRegClass() argument
386 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { in hasBasePointer()
387 const MachineFrameInfo &MFI = MF.getFrameInfo(); in hasBasePointer()
397 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) { in hasBasePointer()
398 if (hasStackRealignment(MF)) in hasBasePointer()
401 if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) { in hasBasePointer()
402 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); in hasBasePointer()
422 bool AArch64RegisterInfo::isArgumentRegister(const MachineFunction &MF, in isArgumentRegister() argument
424 CallingConv::ID CC = MF.getFunction().getCallingConv(); in isArgumentRegister()
425 const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>(); in isArgumentRegister()
426 bool IsVarArg = STI.isCallingConvWin64(MF.getFunction().getCallingConv()); in isArgumentRegister()
485 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { in getFrameRegister()
486 const AArch64FrameLowering *TFI = getFrameLowering(MF); in getFrameRegister()
487 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; in getFrameRegister()
491 const MachineFunction &MF) const { in requiresRegisterScavenging()
496 const MachineFunction &MF) const { in requiresVirtualBaseRegisters()
501 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { in useFPForScavengingIndex()
510 const AArch64FrameLowering &TFI = *getFrameLowering(MF); in useFPForScavengingIndex()
511 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); in useFPForScavengingIndex()
512 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() || in useFPForScavengingIndex()
515 return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE(); in useFPForScavengingIndex()
519 const MachineFunction &MF) const { in requiresFrameIndexScavenging()
524 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { in cannotEliminateFrame()
525 const MachineFrameInfo &MFI = MF.getFrameInfo(); in cannotEliminateFrame()
526 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack()) in cannotEliminateFrame()
558 MachineFunction &MF = *MI->getParent()->getParent(); in needsFrameBaseReg() local
559 const AArch64FrameLowering *TFI = getFrameLowering(MF); in needsFrameBaseReg()
560 MachineFrameInfo &MFI = MF.getFrameInfo(); in needsFrameBaseReg()
580 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) in needsFrameBaseReg()
617 const MachineFunction &MF = *MBB->getParent(); in materializeFrameBaseRegister() local
619 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); in materializeFrameBaseRegister()
623 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
645 const MachineFunction *MF = MI.getParent()->getParent(); in resolveFrameIndex() local
647 MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); in resolveFrameIndex()
716 MachineFunction &MF = *MBB.getParent(); in eliminateFrameIndex() local
717 const MachineFrameInfo &MFI = MF.getFrameInfo(); in eliminateFrameIndex()
719 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); in eliminateFrameIndex()
720 const AArch64FrameLowering *TFI = getFrameLowering(MF); in eliminateFrameIndex()
731 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, in eliminateFrameIndex()
742 StackOffset Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex); in eliminateFrameIndex()
752 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); in eliminateFrameIndex()
765 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true); in eliminateFrameIndex()
767 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
783 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true); in eliminateFrameIndex()
802 MachineFunction &MF) const { in getRegPressureLimit()
803 const AArch64FrameLowering *TFI = getFrameLowering(MF); in getRegPressureLimit()
817 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP in getRegPressureLimit()
818 - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved() in getRegPressureLimit()
819 - hasBasePointer(MF); // X19 in getRegPressureLimit()
846 const MachineFunction &MF) const { in getLocalAddressRegister()
847 const auto &MFI = MF.getFrameInfo(); in getLocalAddressRegister()
848 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects()) in getLocalAddressRegister()
850 else if (hasStackRealignment(MF)) in getLocalAddressRegister()
852 return getFrameRegister(MF); in getLocalAddressRegister()