52                                       unsigned &RegToUseForCFI) const {  in regNeedsCFI()
70 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {  in getCalleeSavedRegs()  argument
112 AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const {  in getDarwinCalleeSavedRegs()  argument
142     const MachineFunction *MF) const {  in getCalleeSavedRegsViaCopy()  argument
151     MachineFunction &MF) const {  in UpdateCustomCalleeSavedRegs()
169                                        unsigned Idx) const {  in getSubClassWithSubReg()
182                                                 CallingConv::ID CC) const {  in getDarwinCallPreservedMask()
210                                           CallingConv::ID CC) const {  in getCallPreservedMask()
250     const MachineFunction &MF) const {  in getCustomEHPadPreservedMask()  argument
266                                                  const uint32_t **Mask) const {  in UpdateCustomCallPreservedMask()  argument
291                                                 CallingConv::ID CC) const {  in getThisReturnPreservedMask()
310 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {  in getReservedRegs()  argument
345                                         MCRegister Reg) const {  in isReservedReg()
349 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {  in isAnyArgRegReserved()  argument
356     const MachineFunction &MF) const {  in emitReservedArgRegCallError()  argument
363                                           MCRegister PhysReg) const {  in isAsmClobberable()
367 bool AArch64RegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {  in isConstantPhysReg()
373                                       unsigned Kind) const {  in getPointerRegClass()
378 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {  in getCrossCopyRegClass()  argument
386 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {  in hasBasePointer()  argument
423                                              MCRegister Reg) const {  in isArgumentRegister()
485 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {  in getFrameRegister()  argument
491     const MachineFunction &MF) const {  in requiresRegisterScavenging()  argument
496     const MachineFunction &MF) const {  in requiresVirtualBaseRegisters()  argument
501 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {  in useFPForScavengingIndex()  argument
519     const MachineFunction &MF) const {  in requiresFrameIndexScavenging()  argument
524 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {  in cannotEliminateFrame()  argument
536                                             int64_t Offset) const {  in needsFrameBaseReg()
601                                              int64_t Offset) const {  in isFrameOffsetLegal()
612                                                   int64_t Offset) const {  in materializeFrameBaseRegister()
635                                             int64_t Offset) const {  in resolveFrameIndex()
683     const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {  in getOffsetOpcodes()
711                                               RegScavenger *RS) const {  in eliminateFrameIndex()
802                                                   MachineFunction &MF) const {  in getRegPressureLimit()
846   const MachineFunction &MF) const {  in getLocalAddressRegister()  argument
859     const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {  in shouldCoalesce()