Lines Matching refs:NewOp

10723 static SDValue tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG,  in tryAdvSIMDModImm64()  argument
10734 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm64()
10744 static SDValue tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG, in tryAdvSIMDModImm32() argument
10776 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS, in tryAdvSIMDModImm32()
10780 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm32()
10792 static SDValue tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG, in tryAdvSIMDModImm16() argument
10816 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS, in tryAdvSIMDModImm16()
10820 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm16()
10832 static SDValue tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op, in tryAdvSIMDModImm321s() argument
10852 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm321s()
10863 static SDValue tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG, in tryAdvSIMDModImm8() argument
10874 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm8()
10884 static SDValue tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG, in tryAdvSIMDModImmFP() argument
10905 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImmFP()
11047 SDValue NewOp; in LowerVectorOR() local
11049 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG, in LowerVectorOR()
11051 (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG, in LowerVectorOR()
11053 return NewOp; in LowerVectorOR()
11055 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG, in LowerVectorOR()
11057 (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG, in LowerVectorOR()
11059 return NewOp; in LowerVectorOR()
11106 SDValue NewOp; in ConstantBuildVector() local
11107 if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) || in ConstantBuildVector()
11108 (NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) || in ConstantBuildVector()
11109 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) || in ConstantBuildVector()
11110 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) || in ConstantBuildVector()
11111 (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) || in ConstantBuildVector()
11112 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits))) in ConstantBuildVector()
11113 return NewOp; in ConstantBuildVector()
11116 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) || in ConstantBuildVector()
11117 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) || in ConstantBuildVector()
11118 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits))) in ConstantBuildVector()
11119 return NewOp; in ConstantBuildVector()
11122 if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) || in ConstantBuildVector()
11123 (NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) || in ConstantBuildVector()
11124 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) || in ConstantBuildVector()
11125 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) || in ConstantBuildVector()
11126 (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) || in ConstantBuildVector()
11127 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits))) in ConstantBuildVector()
11128 return NewOp; in ConstantBuildVector()
11131 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) || in ConstantBuildVector()
11132 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) || in ConstantBuildVector()
11133 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits))) in ConstantBuildVector()
11134 return NewOp; in ConstantBuildVector()
14986 SDValue NewOp; in performANDCombine() local
14989 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG, in performANDCombine()
14991 (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG, in performANDCombine()
14993 return NewOp; in performANDCombine()
14996 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG, in performANDCombine()
14998 (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG, in performANDCombine()
15000 return NewOp; in performANDCombine()
15984 SDValue NewOp = DAG.getNode(N->getOpcode(), DL, HalfVT, NewN0, NewN1); in performVectorAddSubExtCombine() local
15985 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NewOp); in performVectorAddSubExtCombine()
17509 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost; in performPostLD1Combine() local
17510 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops, in performPostLD1Combine()
21307 unsigned NewOp) const { in LowerToPredicatedOp()
21336 if (isMergePassthruOpcode(NewOp)) in LowerToPredicatedOp()
21339 auto ScalableRes = DAG.getNode(NewOp, DL, ContainerVT, Operands); in LowerToPredicatedOp()
21353 if (isMergePassthruOpcode(NewOp)) in LowerToPredicatedOp()
21356 return DAG.getNode(NewOp, DL, VT, Operands, Op->getFlags()); in LowerToPredicatedOp()