3688     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FP_EXTEND_MERGE_PASSTHRU);  in LowerFP_EXTEND()
3700     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FP_ROUND_MERGE_PASSTHRU);  in LowerFP_ROUND()
3734     return LowerToPredicatedOp(Op, DAG, Opcode);  in LowerVectorFP_TO_INT()
3988     return LowerToPredicatedOp(Op, DAG, Opcode);  in LowerVectorINT_TO_FP()
4346     return LowerToPredicatedOp(Op, DAG, AArch64ISD::MUL_PRED);  in LowerMUL()
5323     return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABS_MERGE_PASSTHRU);  in LowerABS()
5410     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FADD_PRED);  in LowerOperation()
5412     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FSUB_PRED);  in LowerOperation()
5414     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMUL_PRED);  in LowerOperation()
5416     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);  in LowerOperation()
5418     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FDIV_PRED);  in LowerOperation()
5420     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FNEG_MERGE_PASSTHRU);  in LowerOperation()
5422     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FCEIL_MERGE_PASSTHRU);  in LowerOperation()
5424     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FFLOOR_MERGE_PASSTHRU);  in LowerOperation()
5426     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FNEARBYINT_MERGE_PASSTHRU);  in LowerOperation()
5428     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FRINT_MERGE_PASSTHRU);  in LowerOperation()
5430     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FROUND_MERGE_PASSTHRU);  in LowerOperation()
5432     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU);  in LowerOperation()
5434     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FTRUNC_MERGE_PASSTHRU);  in LowerOperation()
5436     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FSQRT_MERGE_PASSTHRU);  in LowerOperation()
5438     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FABS_MERGE_PASSTHRU);  in LowerOperation()
5517     return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHS_PRED);  in LowerOperation()
5519     return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHU_PRED);  in LowerOperation()
5572     return LowerToPredicatedOp(Op, DAG,  in LowerOperation()
5588     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMAX_PRED);  in LowerOperation()
5590     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMAXNM_PRED);  in LowerOperation()
5592     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMIN_PRED);  in LowerOperation()
5594     return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMINNM_PRED);  in LowerOperation()
5600     return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABDS_PRED);  in LowerOperation()
5602     return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABDU_PRED);  in LowerOperation()
5606     return LowerToPredicatedOp(Op, DAG, AArch64ISD::BSWAP_MERGE_PASSTHRU);  in LowerOperation()
5608     return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTLZ_MERGE_PASSTHRU);  in LowerOperation()
7863     return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTPOP_MERGE_PASSTHRU);  in LowerCTPOP_PARITY()
7930       return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED);  in LowerMinMax()
7932       return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED);  in LowerMinMax()
7934       return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED);  in LowerMinMax()
7936       return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED);  in LowerMinMax()
7953     return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU);  in LowerBitreverse()
11808     return LowerToPredicatedOp(Op, DAG, PredOpcode);  in LowerDIV()
11944       return LowerToPredicatedOp(Op, DAG, AArch64ISD::SHL_PRED);  in LowerVectorSRA_SRL_SHL()
11958       return LowerToPredicatedOp(Op, DAG, Opc);  in LowerVectorSRA_SRL_SHL()
12090     return LowerToPredicatedOp(Op, DAG, AArch64ISD::SETCC_MERGE_ZERO);  in LowerVSETCC()
21152     return LowerToPredicatedOp(Op, DAG, PredOpcode);  in LowerFixedLengthVectorIntDivideToSVE()
21305 SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,  in LowerToPredicatedOp()  function in AArch64TargetLowering
21777       Op = LowerToPredicatedOp(Op, DAG, RevOp);  in LowerFixedLengthVECTOR_SHUFFLEToSVE()